AM486DX5-133V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133V16BHC Datasheet - Page 52

• Manufacturer Part Number: AM486DX5-133V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

52
If WB/WT meets the necessary setup timing and is sam-
pled Low on the falling edge of RESET, the processor
is placed in Write-through mode and the test register
function is identical to Am486 microprocessors. If WB/
WT meets the necessary setup timing and is sampled
High on the falling edge of RESET, the processor is
placed in Write-back mode and the test registers TR4
and TR5 are modified to support the added write-back
cache functionality. Tables 18 and 19 show the individ-
ual bit functions of these registers. Sections 8.1 and 8.2
provide a detailed description of the field functions.
Note: TR3 has the same functions in both Write-through
and Write-back modes.These functions are identical to
the TR3 register functions provided by Am486 micro-
processors.
7.1
This section includes a detailed description of the bit
fields defined for TR4.
Note: Bits listed in Table 18 as Reserved or Not used
are not included in these descriptions.
EXT=0
EXT=1
Notes:
1. Bit 19 in TR5 is EXT. If EXT = 0, TR4 has the
2. The values of Set State are: 00 = Invalid; 01 = Exclusive; 10 = Modified; 11 = Shared.
Write-Through
Tag (bits 31–12): Read/Write, always available in
Write-through mode. Available only when EXT=0 in
TR5 in Write-back mode. For a cache write, this is
the tag that specifies the address in memory. On a
cache look-up, this is tag for the selected entry in the
cache.
STn (bits 30–29): Read Only, available only in Write-
back mode when Ext=1 in TR5. STn returns the sta-
tus of the set (ST3, ST2, ST1, or ST0) specified by
the TR5 Set State field (bits 18–17) during cache
look-ups. Returned values are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
Write-Back
TR4 Definition
used
Not
31
30–29
STn
Not used
31–20
Rsvd.
28
27–26
ST3
Ext
19
Table 19. Test Register TR5 Bit Descriptions
Table 18. Test Register TR4 Bit Descriptions
Enhanced Am486DX Microprocessor Family
25–24
ST2
Set State
18–17
Not used
Tag
P R E L I M I N A R Y
standard 486
23–22
ST1
21–20
ST0
Reserved
processor definition for write-through cache.
16
Reserved
ST3 (bits 27–26): Read Only, available only in Write-
back mode when Ext=1 in TR5. ST3 returns the sta-
tus of Set 3 during cache look-ups. Returned values
are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
ST2 (bits 25–24): Read Only, available only in Write-
back mode when Ext=1 in TR5. ST2 returns the sta-
tus of Set 2 during cache look-ups. Returned values
are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
ST1 (bits 23–22): Read Only, available only in Write-
back mode when Ext=1 in TR5. ST1 returns the sta-
tus of Set 1 during cache look-ups. Returned values
are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
ST0 (bits 21–20): Read Only, available only in Write-
back mode when Ext=1 in TR5. ST0 returns the sta-
tus of Set 0 during cache look-ups. Returned values
are
— 00 = invalid
— 01 = exclusive
— 10 = modified
— 11 = shared
19–16
Not used
15–12
15–12
Not used
Index
Index
11–4
11
0
Valid
Valid
10
Entry
Entry
3–2
LRU
LRU
9–7
Valid
Valid
6–3
(rd)
(rd)
Control
Control
1–0
used
used
2–0
Not
Not