AM486DX5-133V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133V16BHC Datasheet - Page 54

• Manufacturer Part Number: AM486DX5-133V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

54
6. In TR5, load 0 into the Ext field (bit 19), the required
7.3.3 Example 3: Flushing The Cache
The cache flush mechanism functions in the same way
in Write-back and Write-through modes. Load 11 into
the Control field (bits 1–0) of TR5. All other fields are
ignored, except for Ext in Write-back mode. The cache
flush is triggered by loading the value into TR5. All of
the LRU bits, Valid bits, and Set State bits are cleared.
8
In addition to the new Enhanced Am486DX micropro-
cessors, Am486 microprocessors include the standard
Am486DX, the Am486DE2, and the Enhanced Am486
microprocessor families. Major differences in these pro-
cessors are highlighted in Table 20, and described be-
low.
8.1
The standard Am486DX processor supports an 8-Kbyte
write-through cache. Several important differences exist
between the standard Am486DX processors and the
Am486DE2 and Enhanced processors:
Standard Am486DX processors
Am486DE2 processors
Enhanced Am486 Microprocessor Family
(Am486DX2, Am486DX4)
Enhanced Am486DX Microprocessor Family
(Am486DX2, Am486DX4, Am486DX5)
The ID register contains a different version signa-
ture.
The EADS function performs cache line write-backs
of modified lines to memory in Write-back mode.
A burst write feature is available for copy-backs. The
FLUSH pin and WBINVD instruction copy back all
The other bits in TR4 (9:0) have no effect on the
cache write.
value into the Set State field (bits 18–17) (Write-
back mode only), the required index into the Index
field (bits 10–4), the required entry value into the
Entry field (bits 3–2), and 01 into the Control field
(bits 1–0). Loading the values into TR5 triggers the
cache write. In Write-through mode, the Set State
field is ignored, and the Valid bit (bit 10) in TR4 is
used instead to define the state of the specified set.
Am486 MICROPROCESSOR
FUNCTIONAL DIFFERENCES
Standard Am486DX Processors
Processor
Table 20. Am486 Family Functional Differences
Enhanced Am486DX Microprocessor Family
8-Kbyte write-through
8-Kbyte write-through
8-Kbyte write-back
16-Kbyte write-back
P R E L I M I N A R Y
Cache
8.2
The Am486DE2 processors also provide a 8-Kbyte
write-through cache, and add flexible clock control and
enhanced SMM.
8.3
The Enhanced Am486 microprocessors add support for
write-back cache and 3x clock mode (running at three
times the system bus speed).
8.4
The Enhanced Am486DX microprocessors add support
for 4x clock mode and 16-Kbyte cache. The Enhanced
Am486DX microprocessors are functionally identical to
the Am486DE2 and Enhanced Am486 family proces-
sors except for:
modified data to external memory prior to issuing the
special bus cycle or reset.
The RESET state is invoked either after power up or
after the RESET signal is applied according to the
standard 486DX microprocessor specification.
After reset, the STATUS bits of all lines are set to 0.
The LRU bits of each set are placed in a starting
state.
Nine signals were added to support new features:
CACHE, HITM, INV, SMI, SMIACT, SRESET,
STPCLK, VOLDET, and WB/WT.
The CLKMUL signal was added to support clock-
tripled mode.
The following pins have new functions to implement
write-back cache protocol: AHOLD, BLAST, CLK,
EADS, FLUSH, and PLOCK.
The function of the CLKMUL pin (see page 13) to
set the new clock speed.
The redefinition of TR4 and TR5 to access the 16-
Kbyte cache (see section 7 on page 51).
2x, 3x, 4x
Am486DE2 Microprocessors
Enhanced Am486 Microprocessors
Enhanced Am486DX Microprocessor
Family
Clock
1x, 2x
2x, 3x
2x
Flexible clock control, enhanced SMM
Above plus write-back cache
Above plus 16-Kbyte write-back cache,
extended temperature
Major Enhancements to Standard
DX