AM486DX5-133V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133V16BHC Datasheet - Page 28

• Manufacturer Part Number: AM486DX5-133V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

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3.8.6 Reordering of Write-Backs (AHOLD) with
As seen previously, the Bus Interface Unit (BIU) com-
pletes the processor-initiated access first if the snooping
access occurs after the start of the processor-initiated
access. If the HITM signal occurs one clock cycle before
the ADS = 0 of the processor-initiated access, the write-
back receives priority and is executed first.
However, if the snooping access is executed after the
start of the processor-initiated access, there is a
methodology to reorder the access order. The BOFF
signal delays outstanding processor-initiated cycles so
that a snoop write-back can occur immediately (see
Figure 13).
Scenario : If there are outstanding processor-initiated
cycles on the bus, asserting BOFF clears the bus pipe-
line. If a snoop causes HITM to be asserted, the first
cycle issued by the microprocessor after deassertion of
BOFF is the write-back cycle. After the write-back cycle,
it reissues the aborted cycles. This translates into the
following sequence:
Step 1 The processor starts a cacheable burst read
CLK
ADR
M/IO
CACHE
W/R
ADS
BLAST
BRDY
AHOLD
INV
EADS
HITM
Data
Note:
The circled numbers in this figure represent the steps in section 4.8.5.3.
BOFF
cycle.
from CPU
1
2
3
to CPU
Enhanced Am486DX Microprocessor Family
Figure 12. Snoop Hit Cycle with Write-Back
4
P R E L I M I N A R Y
5
Read
6
Step 2 One clock cycle later, AHOLD is asserted. This
Step 3 Two clock cycles after AHOLD is asserted, the
Step 4 Two clock cycles after EADS is asserted, HITM
Step 5 Note that the processor-initiated access is not
Step 6 With HITM going Low, the core system logic
Step 7 One clock cycle later BOFF is deasserted. The
Step 8 AHOLD is deasserted. In the next clock cycle
7
switches the address bus into an input one clock
cycle after AHOLD is asserted.
EADS and INV signals are asserted to start the
snooping cycle.
becomes valid. The line is modified, therefore
HITM = 0.
completed because BLAST = 1.
asserts BOFF in the next clock cycle to the
snooping processor to reorder the access.
BOFF overrides BRDY. Therefore, the partial
read is not used. It is reread later.
write-back access starts one clock cycle later
because the BOFF has cleared the bus pipe-
line.
the address for the write-back is driven on the
address bus.
W n
W n+4
W n+8
8
W n+C
from CPU
9
10