AM486DX5-133V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133V16BHC Datasheet - Page 41

• Manufacturer Part Number: AM486DX5-133V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

6.3.3 SMRAM
The CPU uses the SMRAM space for state save and
state restore operations during an SMI. The SMI han-
dler, which also resides in SMRAM, uses the SMRAM
space to store code, data, and stacks. In addition, the
SMI handler can use the SMRAM for system manage-
ment information such as the system configuration, con-
figuration of a powered-down device, and system
designer-specific information.
Note: Access to SMRAM is through the CPU internal
cache. To ensure cache consistency and correct oper-
ation, always assert the FLUSH pin in the same clock
as SMI for systems using overlaid SMRAM.
The CPU asserts SMIACT to indicate to the memory
controller that it is operating in System Management
mode. The system logic should ensure that only the
CPU and SMI handler have access to this area. Alter-
nate bus masters or DMA devices trying to access the
SMRAM space when SMIACT is active should be di-
rected to system RAM in the respective area. The sys-
tem logic is minimally required to decode the physical
memory address range 38000h–3FFFFh as SMRAM
area. The CPU saves its state to the state save area
A: Last RDY from non-SMM transfer to SMIACT assertion2 CLKs minimum
B: SMIACT assertion to first ADS for SMM state save
C: SMM state save (dependent on memory performance) 140 CLKs
D: SMI handler
E: SMM state restore (dependent on memory performance)240 CLKs
F: Last RDY from SMM transfer to deassertion of SMIACT2 CLKs minimum
G: SMIACT deassertion of first non-SMM ADS
SMIACT
CLK2
RDY
ADS
CLK
SMI
T1
T2
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
Normal State
Figure 25. SMIACT Timing
A
Clock-Doubled CPU
20 CLKs minimum
User-determined
20 CLKs minimum
B
from 3FFFFh downward to 3FE00h. After saving its
state, the CPU jumps to the address location 38000h to
begin executing the SMI handler. The system logic can
choose to decode a larger area of SMRAM as needed.
The size of this SMRAM can be between 32 Kbyte and
4 Gbyte.The system logic should provide a manual
method for switching the SMRAM into system memory
space when the CPU is not in SMM. This enables ini-
tialization of the SMRAM space (i.e., loading SMI han-
dler) before executing the SMI handler during SMM (see
Figure 26).
space used for
accesses to
State
SMRAM
Save
address
system
loading
C
CPU
Figure 26. Redirecting System Memory
Clock-Tripled CPU
2 CLKs minimum
15 CLKs minimum
100 CLKs
User-determined
180 CLKs
2 CLKs minimum
20 CLKs minimum
D
Handler
SMM
Address to SMRAM
redirected to SMRAM
accesses redirected
E
System memory
System memory
accesses not
to SMRAM
Restore
State
F
Clock-Quadrupled CPU
10 CLKs minimum
70 CLKs
2 CLKs minimum
User-determined
120 CLKs
2 CLKs minimum
20 CLKs minimum
G
Normal
Memory
SMRAM
Normal
State
Space
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