H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 12

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

Rev. 0.5 / Aug. 2010
The mode register contents can be changed using the same command and timing requirements during nor-
mal operation as long as the DRAM in in idle state, i.e. all banks are in the precharged state with tRP satis-
fied, all data bursts are completed and CKE is high prior to writing into the mode register. If the RTT_NOM
Feature is enabled in the Mode Register prior and/or after an MRS Commnad, the ODT Signal must comtinu-
ously be registered LOW ensuring RTT is in an off Stated prior to the MRS command. The ODT Signal may
be registered high after tMOD has expired. If the RTT_NOM Feature is disabled in the Mode Register prior
and after an MRS command, the ODT Signal can be registred either LOW or HIGH before, during and after
the MRS command. The mode registers are divided into various fields depending on the functionality and/or
modes.
ADDRESS
Seetings
CMD
CKE
ODT
ODT
CK#
CK
RTT_Nom ENABLED prior and/or after MRS command
RTT_Nom DISENABLED prior and/or after MRS command
VALID
VALID
VALID
VALID
T0
VALID
VALID
VALID
VALID
Old Settings
T1
VALID
VALID
VALID
T2
ODTLoff+1
VALID
VALID
MRS
Ta0
Figure 5. tMOD Timing
/DES
VALID
VALID
NOP
Ta1
/DES
VALID
VALID
NOP
Ta2
Updating Settings
tMOD
/DES
VALID
VALID
NOP
Ta3
VALID
VALID
/DES
NOP
Ta4
TIME BREAK
/DES
VALID
VALID
NOP
Tb0
VALID
VALID
VALID
Tb1
H5TQ2G63BFR
New Settings
DON’T CARE
VALID
VALID
VALID
VALID
Tb2
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