H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 22

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

Rev. 0.5 / Aug. 2010
1.10.1 Multi Purpose Register
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit
sequence. The basic concept of the MPR is shown in Figure 10.
The enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2=1,
as shown in Table 5. Prior to issuing the MRS command, all banks must be in the idle in the idle state (all
banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands will be
redirected to the Multi Purpose Register. The resulting operation when a RD or RDA command is issued is
defined by MR3 bits A[1:0] when the MPR is enabled as shown in Table 6. When the MPR is enabled, only
RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled(MR3
bit A2=0). Note that in MPR mode RDA has the same functionality as a READ command which means the
auto precharge part of RDA is ignored. Power-Down mode, Self-Refresh, and any other non-RD/RDA com-
mand is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode.
MR3 A[2]
MPR
0b
1b
(all banks precharged)
MR3 A[1:0]
don’t care
(0b or 1b)
MPR-Loc
Table 12
Memory Core
See
Table 5. MPR MR3 Register Definition
Enable MPR mode, subsequent RD/RDA commands defined by MR3
Figure 10. MPR Block Diagram
MR3[A2]
DQ, DM, DQS, DQS#
All subsequent Reads will come from DRAM array.
All subsequent Write will go to DRAM array.
Normal operation, no MPR transaction.
Pre-defined data for Reads
Function
A[1:0]
Multi purpose register
H5TQ2G63BFR
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