H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 20

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

H5TQ2G63BFR
1.8.1 Partial Array Self-Refresh (PASR)
Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to detemine if
DDR3 SDRAM devices support the following options or requirements referred to in this material. If PASR (Partial Array
Self-Refresh) is enabled, data located in areas of the array beyond the specified address range shown in Figure 8 wil be
maintains if tREFI conditions are met and no Self-Refresh command is issued.
1.8.2 CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5), as shown in Figure 8. CAS Write Latency is the delay, in clock
cycles, between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not sup-
port any half clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency
(CWL); WL = AL + CWL. For detailed Write operation refer to “WRITE Operation”.
1.8.3 Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)
Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determaine if
DDR3 SDRAM devices support the following options or requirements referred to in this material. DDR3 SDRAM’s must
support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the
Extended Temperature Range must use the optional ASR function or program the SRT bit appropriately.
1.8.4 Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal integ-
rity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an
MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT setings. In Write leveling mode, only
RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”.
Rev. 0.5 / Aug. 2010
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