H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 36

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

Rev. 0.5 / Aug. 2010
5.4 Slew Rate Definitions for Single Ended Input Signals
5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VRef and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VRef and the first crossing of VIL (AC) max.
5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max
and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew
rate between the last crossing of VIH (DC) min and the first crossing of VRef.
Input slew rate for rising edge
Input slew rate for falling edge
Input slew rate for rising edge
Input slew rate for falling edge VIH (DC) min
Description
P a r t A : S e t u p
P a r t B : H o l d
Input Nominal Slew Rate Definition for Single-Ended Signals
F i g u r e 8 2 ? I n p u t N o m i n a l S l e w R a t e D e f i n i t i o n f o r S i n g l e - E n d e d S i g n a l s
Single-Ended Input Slew Rate Definition
D e l t a T F H
VIL (DC) max
D e l t a T F S
Vref
Vref
Min
Measured
VIL (AC) max
VIH (AC) min
Max
Vref
Vref
D e l t a T R H
D e l t a T R S
Vref-VIL (AC) max
Vref-VIL (DC) max
VIH (AC) min-Vref
VIH (DC) min-Vref
Defined by
Delta TRS
Delta TRH
Delta TFS
Delta TFH
v I H ( A C ) m i n
v I H ( A C ) m i n
v I H ( D C ) m i n
v I H ( D C ) m i n
v I H ( A C ) m a x
v I H ( A C ) m a x
v I H ( D C ) m a x
v I H ( D C ) m a x
v R e f D Q o r
v R e f D Q o r
v R e f C A
v R e f C A
H5TQ2G63BFR
Applicable for
(tIH, tDH)
(tIS, tDS)
Setup
Hold
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