XCV600E-6BGG432C Xilinx Inc, XCV600E-6BGG432C Datasheet
XCV600E-6BGG432C
Specifications of XCV600E-6BGG432C
Available stocks
Related parts for XCV600E-6BGG432C
XCV600E-6BGG432C Summary of contents
Page 1
R DS022-1 (v2.3) July 17, 2002 Features • Fast, High-Density 1.8 V FPGA Family - Densities from system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant ...
Page 2
... System Device Gates Gates XCV50E 71,693 20,736 XCV100E 128,236 32,400 XCV200E 306,393 63,504 XCV300E 411,955 82,944 XCV400E 569,952 129,600 XCV600E 985,882 186,624 XCV1000E 1,569,178 331,776 XCV1600E 2,188,742 419,904 XCV2000E 2,541,952 518,400 XCV2600E 3,263,755 685,584 XCV3200E 4,074,387 876,096 Virtex-E Compared to Virtex Devices The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family ...
Page 3
R resources. The abundance of routing resources permits the Virtex-E family to accommodate even the largest and most complex designs. Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Con- figuration data can be ...
Page 4
... Changed several pins to “No Connect in the XCV100E“ and removed duplicate V pins in Table ~ (Module 4). • Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4). • Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4). • Corrected pair 18 in Table 75 (Module “AO in the XCV1000E, XCV1600E“. Module ...
Page 5
... Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and XCV2000E devices. • Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices. • Revised Table 62 to include pinout information for the XCV400E and XCV600E devices in the BG560 package. ...
Page 6
Virtex™-E 1.8 V Field Programmable Gate Arrays Module www.xilinx.com 1-800-255-7778 R DS022-1 (v2.3) July 17, 2002 Production Product Specification ...
Page 7
R DS022-2 (v2.8) January 16, 2006 Architectural Description Virtex-E Array The Virtex-E user-programmable gate array, shown in Figure 1, comprises two major configurable elements: con- figurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for ...
Page 8
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 1: Supported I/O Standards I/O Output Input Standard V V CCO CCO LVTTL 3.3 3.3 LVCMOS2 2.5 2.5 LVCMOS18 1.8 1.8 SSTL3 I & II 3.3 N/A SSTL2 I & II 2.5 ...
Page 9
R Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure multiple V pins, all of which must be connected to the CCO same voltage. This voltage is determined by the output ...
Page 10
Virtex™-E 1.8 V Field Programmable Gate Arrays G4 G3 LUT LUT F5IN CLK CE Storage Elements The storage elements in the ...
Page 11
... Table 4 is available in each Virtex-E device. Table 4: Virtex-E Block SelectRAM Amounts Virtex-E Device # of Blocks Block SelectRAM Bits XCV50E XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E Dedicated Routing. XCV1600E XCV2000E XCV2600E XCV3200E As illustrated in fully synchronous dual-ported (True Dual Port) 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured indepen- dently, providing built-in bus-width conversion ...
Page 12
Virtex™-E 1.8 V Field Programmable Gate Arrays RAMB4_S#_S# WEA ENA DOA[#:0] RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB DOB[#:0] CLKB ADDRB[#:0] DIB[#:0] Figure 6: Dual-Port Block SelectRAM Table 5 shows the depth and width aspect ratios for the block SelectRAM. ...
Page 13
R Dedicated Routing Some classes of signal require dedicated routing resources to maximize performance. In the Virtex-E architecture, dedi- cated routing resources are provided for two classes of signal. • Horizontal routing resources are provided for on-chip 3-state buses. Four ...
Page 14
Virtex™-E 1.8 V Field Programmable Gate Arrays The DLL also operates as a clock mirror. By driving the out- put from a DLL off-chip and then back on again, the DLL can be used to deskew a board level clock ...
Page 15
R IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI Instruction Set The Virtex-E series Boundary Scan instruction set also includes instructions to configure the device and read back configuration data (CFG_IN, CFG_OUT, and JSTART). ...
Page 16
... Table 7: IDCODEs Assigned to Virtex-E FPGAs FPGA XCV50E XCV100E XCV200E Figure 12. XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E Note: Attempting to load an incorrect bitstream causes configuration to fail and can damage the device. Including Boundary Scan in a Design ...
Page 17
R Development System Virtex-E FPGAs are supported by the Xilinx Foundation and Alliance Series CAE tools. The basic methodology for Virtex-E design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and ...
Page 18
Virtex™-E 1.8 V Field Programmable Gate Arrays For in-circuit debugging, an optional download and read- back cable is available. This cable connects the FPGA in the target system workstation. After downloading the design into the FPGA, ...
Page 19
... Table 9: Virtex-E Bitstream Lengths Device # of Configuration Bits XCV50E XCV100E XCV200E 1,442,016 XCV300E 1, 875,648 XCV400E 2,693,440 XCV600E 3,961,632 XCV1000E 6,587,520 XCV1600E 8,308,992 XCV2000E 10,159,648 XCV2600E 12,922,336 XCV3200E 16,283,712 Slave-Serial Mode In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other source of serial configuration data ...
Page 20
Virtex™-E 1.8 V Field Programmable Gate Arrays . Optional Pull-up 1 Resistor on Done PROGRAM Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 Ω should be added to ...
Page 21
R Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases Release INIT INIT when finished. INIT? Load a Configuration Bit Once per bitstream, FPGA checks data using CRC and ...
Page 22
Virtex™-E 1.8 V Field Programmable Gate Arrays 3. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance instead ...
Page 23
R Apply Power FPGA starts to clear configuration memory. PROGRAM from Low to High FPGA makes a final clearing pass and releases INIT when finished. Release INIT INIT? Set WRITE = Low Enter Data Source Set CS = Low Apply ...
Page 24
Virtex™-E 1.8 V Field Programmable Gate Arrays Configuration through the TAP uses the CFG_IN instruc- tion. This instruction allows data input on TDI to be con- verted into data packets for the internal configuration bus. The following steps are required ...
Page 25
R the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed. In addi- tion, the GTS, GSR, and GWE events can be made depen- ...
Page 26
Virtex™-E 1.8 V Field Programmable Gate Arrays CLKDLL CLKIN CLK0 CLK90 CLKFB CLK180 CLK270 CLK2X CLKDV RST LOCKED Figure 22: Standard DLL Symbol CLKDLL CLKDLLHF CLKIN CLK0 CLKFB CLK180 CLKDV RST LOCKED ds022_027_121099 Figure 23: High Frequency DLL Symbol CLKDLLHF ...
Page 27
R ground. As the DLL delay taps reset to zero, glitches can occur on the DLL clock output pins. Activation of the RST pin can also severely affect the duty cycle of the clock out- put pins. Furthermore, the DLL ...
Page 28
Virtex™-E 1.8 V Field Programmable Gate Arrays DLL Properties Properties provide access to some of the Virtex-E series DLL features, (for example, clock division and duty cycle correction). Duty Cycle Correction Property The 1x clock outputs, CLK0, CLK90, CLK180, and ...
Page 29
R Useful Application Examples The Virtex-E DLL can be used in a variety of creative and useful applications. The following examples show some of the more common applications. The Verilog and VHDL example files are available at: ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip Standard Usage ...
Page 30
Virtex™-E 1.8 V Field Programmable Gate Arrays Because any single DLL can access only two BUFGs at most, any additional output clock signals must be routed from the DLL in this example on the high speed backbone routing. The dll_2x ...
Page 31
R RAMB4_S#_S# WEA ENA DOA[#:0] RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB DOB[#:0] CLKB ADDRB[#:0] DIB[#:0] Figure 31: Dual-Port Block SelectRAM+ Memory RAMB4_S RST DO[#:0] CLK ADDR[#:0] DI[#:0] ds022_033_121399 Figure 32: Single-Port Block SelectRAM+ Memory Table 14: Available ...
Page 32
Virtex™-E 1.8 V Field Programmable Gate Arrays Data Output Bus—DO[A|B]<#:0> The data out bus reflects the contents of the memory cells referenced by the address bus at the last active clock edge. During a write operation, the data out bus ...
Page 33
R indicating that the block SelectRAM+ memory is now dis- abled. The DO bus retains the last value. Dual Port Timing Figure 34 shows a timing diagram for a true dual-port read/write block SelectRAM+ memory. The clock on port A ...
Page 34
Virtex™-E 1.8 V Field Programmable Gate Arrays CLK_A ADDR_A EN_A WE_A DI_A DO_A CLK_B ADDR_B 00 EN_B WE_B DI_B 1111 DO_B MEM (00) Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory At the third rising edge ...
Page 35
R Initialization in Verilog and Synopsys The block SelectRAM+ structures can be initialized in Verilog for both simulation and synthesis for inclusion in the EDIF output file. The simulation of the Verilog code uses a def- param to pass the ...
Page 36
Virtex™-E 1.8 V Field Programmable Gate Arrays VHDL Initialization Example library IEEE; use IEEE.std_logic_1164.all; entity MYMEM is port (CLK, WE:in std_logic; ADDR: in std_logic_vector(8 downto 0); DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic_vector(7 downto 0)); end MYMEM; architecture BEHAVE ...
Page 37
R Verilog Initialization Example module MYMEM (CLK, WE, ADDR, DIN, DOUT); input CLK, WE; input [8:0] ADDR; input [7:0] DIN; output [7:0] DOUT; wire logic0, logic1; //synopsys dc_script_begin //set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string //set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string ...
Page 38
Virtex™-E 1.8 V Field Programmable Gate Arrays Fundamentals Modern bus applications, pioneered by the largest and most influential companies in the digital electronics industry, are commonly introduced with a new I/O standard tailored spe- cifically to the needs of that ...
Page 39
R standard requires a Differential Amplifier input buffer and a Push-Pull output buffer. SSTL3 — Stub Series Terminated Logic for 3.3V The Stub Series Terminated Logic for 3.3V, or SSTL3 stan- dard is a general purpose 3.3V memory bus standard ...
Page 40
Virtex™-E 1.8 V Field Programmable Gate Arrays The voltage reference signal is “banked” within the Virtex-E device on a half-edge basis such that for all packages there are eight independent V banks internally. See REF for a representation of the ...
Page 41
R represents a combination of the LVTTL IBUFG and BUFG symbols, such that the output of the BUFGP can connect directly to the clock pins throughout the design. Unlike previous architectures, the Virtex-E BUFGP symbol can only be placed in ...
Page 42
Virtex™-E 1.8 V Field Programmable Gate Arrays LVTTL 3-state output buffers have selectable drive strengths. The format for LVTTL OBUFT symbol names is as follows: OBUFT_<slew_rate>_<drive_strength> where <slew_rate> is either F (Fast (Slow), and <drive_strength> is specified in ...
Page 43
R IOBUF x133_06_111699 Figure 42: Input/Output Buffer Symbol (IOBUF) The following list details variations of the IOBUF symbol. • IOBUF • IOBUF_S_2 • IOBUF_S_4 • IOBUF_S_6 • IOBUF_S_8 • IOBUF_S_12 • IOBUF_S_16 • IOBUF_S_24 • IOBUF_F_2 ...
Page 44
Virtex™-E 1.8 V Field Programmable Gate Arrays IOB Flip-Flop/Latch Property The Virtex-E series I/O Block (IOB) includes an optional register on the input path, an optional register on the output path, and an optional register on the 3-state control pin. ...
Page 45
R Input termination techniques include the following. • None • Parallel (Shunt) These termination techniques can be applied in any combi- nation. A generic example of each combination of termina- tion methods appears in Figure 43. Unterminated Double Parallel Terminated ...
Page 46
... HSTL Class III HSTL Class IV SSTL2 Class I SSTL2 Class II SSTL3 Class I SSTL3 Class II CTT AGP Note: This analysis assumes load for each output. Table 22: Virtex-E Equivalent Power/Ground Pairs Pkg/Part XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E CS144 12 PQ240 20 HQ240 BG352 20 BG432 BG560 (1) ...
Page 47
R Application Examples Creating a design with the SelectI/O features requires the instantiation of the desired library symbol within the design code. At the board level, designers need to know the termi- nation techniques required for each I/O standard. This ...
Page 48
Virtex™-E 1.8 V Field Programmable Gate Arrays HSTL A sample circuit illustrating a valid termination technique for HSTL_I appears in Figure 46. A sample circuit illustrating a valid termination technique for HSTL_III appears in Figure 47. Table 25: HSTL Class ...
Page 49
R SSTL3_I A sample circuit illustrating a valid termination technique for SSTL3_I appears in Figure 49. DC voltage specifications appear in Table 28. SSTL3 Class 3.3V CCO 50Ω 25Ω 1.5V ...
Page 50
Virtex™-E 1.8 V Field Programmable Gate Arrays SSTL2_II A sample circuit illustrating a valid termination technique for SSTL2_II appears in Figure 52. DC voltage specifications appear in Table 31. SSTL2 Class 1.25V 2.5V CCO ...
Page 51
R LVTTL LVTTL requires no termination. DC voltage specifications appears in Table 34. Table 34: LVTTL Voltage Specifications Parameter Min V 3.0 CCO V - REF 2.0 IH −0 2 ...
Page 52
Virtex™-E 1.8 V Field Programmable Gate Arrays LVDS Depending on whether the device is transmitting an LVDS signal or receiving an LVDS signal, there are two different circuits used for LVDS termination. A sample circuit illustrat- ing a valid termination ...
Page 53
R Termination Resistor Packs Resistor packs are available with the values and the config- uration required for LVDS and LVPECL termination from Bourns, Inc., as listed in Table. For pricing and availability, please contact Bourns directly at http://www.bourns.com Table 40: ...
Page 54
Virtex™-E 1.8 V Field Programmable Gate Arrays Optional N-side Some designers might prefer to also instantiate the N-side buffer for the global clock buffer. This allows the top-level net list to include net connections for both PCB layout and sys- ...
Page 55
R Table 42: Input Library Macros Name Inputs IBUFDS_FD_LVDS I, IB, C IBUFDS_FDE_LVDS I, IB, CE, C IBUFDS_FDC_LVDS I, IB, C, CLR IBUFDS_FDCE_LVDS I, IB, CE, C, CLR IBUFDS_FDP_LVDS I, IB, C, PRE IBUFDS_FDPE_LVDS I, IB, CE, C, PRE IBUFDS_FDR_LVDS ...
Page 56
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 43: Output Library Macros Name Inputs OBUFDS_FD_LVDS D, C OBUFDS_FDE_LVDS DD, CE, C OBUFDS_FDC_LVDS D, C, CLR OBUFDS_FDCE_LVDS D, CE, C, CLR OBUFDS_FDP_LVDS D, C, PRE OBUFDS_FDPE_LVDS D, CE, C, PRE OBUFDS_FDR_LVDS ...
Page 57
R The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the “map -pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b” is both inputs ...
Page 58
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 44: Bidirectional I/O Library Macros Name IOBUFDS_FD_LVDS IOBUFDS_FDE_LVDS IOBUFDS_FDC_LVDS IOBUFDS_FDCE_LVDS IOBUFDS_FDP_LVDS IOBUFDS_FDPE_LVDS IOBUFDS_FDR_LVDS IOBUFDS_FDRE_LVDS IOBUFDS_FDS_LVDS IOBUFDS_FDSE_LVDS IOBUFDS_LD_LVDS IOBUFDS_LDE_LVDS IOBUFDS_LDC_LVDS IOBUFDS_LDCE_LVDS IOBUFDS_LDP_LVDS IOBUFDS_LDPE_LVDS Revision History The following table shows the revision history for ...
Page 59
... Table ~ (Module 4). Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4). Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4). Corrected pair 18 in Table 75 (Module “AO in the XCV1000E, XCV1600E“. Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to Preliminary ...
Page 60
Virtex™-E 1.8 V Field Programmable Gate Arrays Virtex-E Data Sheet The Virtex-E Data Sheet contains the following modules: • DS022-1, Virtex-E 1.8V FPGAs: Introduction and Ordering Information (Module 1) • DS022-2, Virtex-E 1.8V FPGAs: Functional Description (Module 2) Module 2 ...
Page 61
... Virtex-E device with a corresponding speed file designation. Table 1: Virtex-E Device Speed Grade Designations Speed Grade Designations Device Advance XCV50E XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E All specifications are subject to change without notice. www.xilinx.com 1-800-255-7778 Preliminary Production – ...
Page 62
Virtex™-E 1.8 V Field Programmable Gate Arrays DC Characteristics Absolute Maximum Ratings Symbol V Internal Supply voltage relative to GND CCINT V Supply voltage relative to GND CCO V Input Reference Voltage REF (3) V Input voltage relative to GND ...
Page 63
... XCV1000E 500 mA XCV1600E 500 mA XCV2000E 500 mA XCV2600E 500 mA XCV3200E 500 mA XCV50E 2 mA XCV100E 2 mA XCV200E 2 mA XCV300E 2 mA XCV400E 2 mA XCV600E 2 mA XCV1000E 2 mA XCV1600E 2 mA XCV2000E 2 mA XCV2600E 2 mA XCV3200E 2 mA μA All –10 +10 All 8 pF All Note 2 0.25 mA Note 2 ...
Page 64
... This is the time required to reach the nominal 1 power supply voltage of the device ramp rate nominal voltage in 50 ms. For more details on power supply requirements, see XAPP158 on www.xilinx.com. Product (Commercial Grade) XCV50E - XCV600E XCV812E - XCV2000E XCV2600E - XCV3200E Virtex-E Family, Industrial Grade Notes: 1. ...
Page 65
Input/Output Standard V, Min V, Max CTT – 0.5 V REF AGP – 0.5 V REF Notes and V for lower drive currents are sample tested Tested according to the relevant specifications. ...
Page 66
... XCV3200E 0.55 T All 0.8 IOPLI T XCV50E 1.31 IOPLID XCV100E 1.31 XCV200E 1.39 XCV300E 1.39 XCV400E 1.43 XCV600E 1.55 XCV1000E 1.55 XCV1600E 1.59 XCV2000E 1.59 XCV2600E 1.59 XCV3200E 1.59 www.xilinx.com 1-800-255-7778 2. For other standards, adjust the delays with the 8. (1) Speed Grade ...
Page 67
... Virtex™-E 1.8 V Field Programmable Gate Arrays Symbol Device Min T All 0. 0. 0.18 IOCKIQ T / IOPICK All 0. IOICKP T / XCV50E 1. IOPICKD T IOICKPD XCV100E 1. XCV200E 1. XCV300E 1. XCV400E 1. XCV600E 1. XCV1000E 1. XCV1600E 1. XCV2000E 1. XCV2600E 1. XCV3200E 1. All 0.28 / IOICECK T 0.0 IOCKICE T All 0.38 IOSRCKI T All 0.54 IOSRIQ T All 3.88 GSRQ Table www.xilinx.com 1-800-255-7778 (1) ...
Page 68
Virtex™-E 1.8 V Field Programmable Gate Arrays IOB Input Switching Characteristics Standard Adjustments Description Data Input Delay Adjustments Standard-specific data input delay adjustments Notes: 1. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see ...
Page 69
R IOB Output Switching Characteristics, Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in (2) Description Propagation Delays O input ...
Page 70
Virtex™-E 1.8 V Field Programmable Gate Arrays IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values ...
Page 71
R Calculation Function of Capacitance ioop T is the propagation delay from the O Input of the IOB to ioop the pad. The values for T are based on the standard ioop capacitive load (C ) ...
Page 72
Virtex™-E 1.8 V Field Programmable Gate Arrays Clock Distribution Switching Characteristics Description GCLK IOB and Buffer Global Clock PAD to output. Global Clock Buffer I input to O output I/O Standard Global Clock Input Adjustments Description Data Input Delay Adjustments ...
Page 73
R CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used, see worst-case. Precise values are provided by the timing analyzer. Description Combinatorial Delays 4-input function: F/G inputs to X/Y outputs 5-input function: F/G inputs ...
Page 74
Virtex™-E 1.8 V Field Programmable Gate Arrays F5IN CLK CE Module COUT LUT ...
Page 75
R CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Description Combinatorial Delays F operand inputs to X ...
Page 76
Virtex™-E 1.8 V Field Programmable Gate Arrays CLB Distributed RAM Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs (WE active mode Clock CLK to X/Y outputs (WE active mode Shift-Register Mode Clock ...
Page 77
R Block RAM Switching Characteristics Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times before Clock CLK ADDR inputs DIN inputs EN input RST input WEN input Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low ...
Page 78
... DLL output jitter is already included in the timing calculation. Module Symbol Device T XCV50E ICKOFDLL XCV100E IOB XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E threshold with 35 pF external capacitive load. For other I/O standards and different loads, see CC www.xilinx.com 1-800-255-7778 (2, 3) Speed Grade Min ...
Page 79
... Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Symbol Device T XCV50E ICKOF XCV100E IOB XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E threshold with 35 pF external capacitive load. For other I/O standards and different loads, see CC www.xilinx.com 1-800-255-7778 (2) Speed Grade ...
Page 80
... XCV300E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV400E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV600E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV1000E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV1600E 1.5 / – ...
Page 81
... DS022-3 (v2.9.2) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Symbol Device Min IOB Input Switching XCV50E 1 PSFD PHFD XCV100E 1 XCV200E 1 XCV300E 2 XCV400E 2 XCV600E 2 XCV1000E 2 XCV1600E 2 XCV2000E 2 XCV2600E 2 XCV3200E 2 www.xilinx.com 1-800-255-7778 (2, 3) Speed Grade - Units ...
Page 82
Virtex™-E 1.8 V Field Programmable Gate Arrays DLL Timing Parameters All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect ...
Page 83
R DLL Clock Tolerance, Jitter, and Phase Information All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. Description Input Clock Period Tolerance Input Clock Jitter Tolerance ...
Page 84
... Table ~ (Module 4). • Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4). • Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4). • Corrected pair 18 in Table 75 (Module “AO in the XCV1000E, XCV1600E“. • Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to 11/20/00 1 ...
Page 85
R Date Version • Under 07/23/01 2.2 • Changes made to SSTL symbol names in Standard Adjustments • Removed T 07/26/01 2.3 • Reworded power supplies footnote to 9/18/01 2.4 • Updated the speed grade designations used in data sheets, ...
Page 86
Virtex™-E 1.8 V Field Programmable Gate Arrays Module www.xilinx.com 1-800-255-7778 R DS022-3 (v2.9.2) March 14, 2003 Production Product Specification ...
Page 87
R DS022-4 (v2.5) March 14, 2003 Virtex-E Pin Definitions Pin Name Dedicated Pin GCK0, GCK1, Yes GCK2, GCK3 M0, M1, M2 Yes CCLK Yes PROGRAM Yes DONE Yes INIT No BUSY/DOUT No D0/DIN, No D1, D2, D3, D4, D5, D6, ...
Page 88
... This change also requires one Virtex I/O or VREF pin to be swapped with a standard I/O pin. Additionally, accommodating differential clock input pairs in Virtex-E caused some IO_V and XCV600E devices only. Virtex IO_V P87 are Virtex-E IO_V REF Virtex-E pins P215 and P87 are IO_DLL. ...
Page 89
R Low Voltage Differential Signals The Virtex-E family incorporates low-voltage signalling (LVDS and LVPECL). Two pins are utilized for these signals to be connected to a Virtex-E device. These are known as differential pin pairs. Each differential pin pair has ...
Page 90
Virtex™-E 1.8 V Field Programmable Gate Arrays CS144 Chip-Scale Package XCV50E, XCV100E, XCV200E, XCV300E and XCV400E devices in CS144 Chip-scale packages have footprint com- patibility. In the CS144 package, bank pairs that share a side are internally interconnected, permitting four ...
Page 91
R Table 4: CS144 — XCV50E, XCV100E, XCV200E Bank Pin Description 4 IO_L15N_YY 4 IO_L15P_YY 4 IO_L16N_YY 4 IO_VREF_L16P_YY 4 IO_L17N_YY 4 IO_L17P_YY 4 IO_LVDS_DLL_L18P 4 IO_VREF 4 IO_VREF 4 IO_VREF 5 GCK1 IO_LVDS_DLL_L18N 5 IO_L19N_YY 5 ...
Page 92
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 4: CS144 — XCV50E, XCV100E, XCV200E Bank Pin Description 1 VCCO 1 VCCO 2 VCCO 3 VCCO 3 VCCO 4 VCCO 5 VCCO 5 VCCO 6 VCCO 7 VCCO 7 VCCO NA ...
Page 93
R Table 5: CS144 Differential Pin Pair Summary XCV50E, XCV100E, XCV200E P N Pair Bank Pin Pin ...
Page 94
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 6: PQ240 — XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Pin # Pin Description P173 IO_L16N_Y P171 IO_VREF_L17P_Y P170 IO_L17N_Y P169 IO 1 P168 IO_VREF_L18P_Y P167 IO_D1_L18N_Y P163 IO_D2_L19P_YY P162 IO_L19N_YY P161 IO P160 ...
Page 95
R Table 6: PQ240 — XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Pin # Pin Description P74 IO_L43P_YY 1 P73 IO_VREF_L43N_YY P72 IO P71 IO_L44P_YY P70 IO_VREF_L44N_YY P68 IO_L45P_YY P67 IO_L45N_YY 2 P66 IO_VREF_L46P_Y P65 IO_L46N_Y P64 IO_L47P_YY P63 IO_L47N_YY P57 IO_L48N_YY ...
Page 96
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 6: PQ240 — XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Pin # Pin Description P137 VCCINT P104 VCCINT P88 VCCINT P77 VCCINT P43 VCCINT P32 VCCINT P16 VCCINT P240 VCCO P232 VCCO P226 VCCO ...
Page 97
R PQ240 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the pin pair can be used as ...
Page 98
... AO in the XCV50E, 200E, 400E the XCV100E. Module HQ240 High-Heat Quad Flat-Pack Packages XCV600E and XCV1000E devices in High-heat dissipation Other Quad Flat-pack packages have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless AO Functions device-dependent as indicated in the footnotes. If the pin is √ ...
Page 99
... TDO P180 VCCO P179 CCLK P178 IO_DOUT_BUSY_L15P_YY P177 IO_DIN_D0_L15N_YY P176 VCCO P175 IO_VREF DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 8: HQ240 — XCV600E, XCV1000E Bank Pin # 1 P174 1 P173 1 P172 1 P171 IO_VREF_L17P_Y 1 P170 1 P169 ...
Page 100
... P113 IO_L33N_YY P112 GND P111 IO_VREF_L34P_YY P110 IO_L34N_YY P109 IO_VREF P108 IO_VREF_L35P_YY P107 IO_L35N_YY P106 GND P105 VCCO P104 VCCINT P103 IO_L36P_YY Module Table 8: HQ240 — XCV600E, XCV1000E Bank Pin # 3 P102 1 NA P101 3 P100 NA P99 3 P98 3 P97 IO_VREF_L38P_Y 3 P96 3 P95 3 P94 NA ...
Page 101
... P37 GND P36 IO_VREF_L54N_Y P35 IO_L54P_Y P34 IO_L55N_Y P33 IO_VREF_L55P_Y P32 VCCINT P31 IO DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 8: HQ240 — XCV600E, XCV1000E Bank Pin # 5 P30 5 P29 5 P28 5 P27 NA P26 5 P25 NA P24 ...
Page 102
... P203 9 1 P199 P200 10 1 P194 P195 11 1 P191 P192 12 1 P188 P189 13 1 P186 P187 14 1 P184 P185 15 2 P178 P177 Module Table 9: HQ240 Differential Pin Pair Summary XCV600E, XCV1000E Pair Other 24 AO Functions _DLL_L40P _DLL_L40N _DLL_L6P _DLL_L6N VREF 32 √ ...
Page 103
... Note the XCV600E. DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays BG352 Ball Grid Array Packages XCV100E, XCV200E, and XCV300E devices in BG352 Ball Other Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless ...
Page 104
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description IO_LVDS_DLL_L9N 0 GCK3 1 GCK2 1 IO_LVDS_DLL_L9P IO_L10N 1 IO_L10P 1 IO_L11N_Y 1 IO_VREF_1_L11P_Y 1 ...
Page 105
R Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description 2 IO_D3_L30N _Y 2 IO_L31P 2 IO_L31N IO_L32P_YY 2 IO_L32N_YY IO_L33P 3 IO_L33N 3 IO_D4_L34P _Y 3 IO_VREF_3_L34N _Y 3 IO_L35P_YY ...
Page 106
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description 4 IO_VREF_4_L53P_Y 4 IO_L53N_Y 4 IO_L54P 4 IO_L54N IO_LVDS_DLL_L55P 4 GCK0 5 GCK1 5 IO_LVDS_DLL_L55N ...
Page 107
R Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description 6 IO_L74P _Y 6 IO_L75N 6 IO_L75P IO_L76N_YY 7 IO_L76P_YY IO_L77N 7 IO_L77P 7 IO_L78N _Y 7 IO_VREF_7_L78P _Y 7 IO_L79N_YY ...
Page 108
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 10: BG352 — XCV100E, XCV200E, XCV300E Bank Pin Description NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT 0 VCCO 0 VCCO 0 VCCO 1 VCCO 1 VCCO 1 VCCO 2 ...
Page 109
R BG352 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A check (√) in the AO column indicates that the pin pair can be used ...
Page 110
... AO in the XCV100E the XCV200E. Module BG432 Ball Grid Array Packages XCV300E, XCV400E, and XCV600E devices in BG432 Ball Other Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless AO Functions device-dependent as indicated in the footnotes. If the pin is √ ...
Page 111
... IO_L22P_YY 1 IO_L23N_YY 1 IO_L23P_YY 1 IO_L24N_YY 1 IO_VREF_L24P_YY 1 IO_L25N_Y 1 IO_VREF_L25P_Y 1 IO_L26N_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 12: BG432 — XCV300E, XCV400E, XCV600E Pin # Bank Pin Description A20 1 D19 1 B19 1 IO_VREF_L27P_YY A19 1 B18 1 D18 1 2 C18 ...
Page 112
... IO_L45N_Y 2 IO_L46P_Y 2 IO_L46N_Y 2 IO_L47P_Y 2 IO_L47N_Y 2 IO_VREF_L48P_YY 2 IO_D3_L48N_YY 2 IO_L49P_Y 2 IO_L49N_Y 2 IO_VREF_L50P_Y 2 IO_L50N_Y 2 IO_L51P_YY 2 IO_L51N_YY IO_L52P_Y 3 IO_VREF_L52N_Y 3 IO_L53P_Y 3 IO_L53N_Y 3 IO_D4_L54P_YY 3 IO_VREF_L54N_YY 3 IO_L55P_Y 3 IO_L55N_Y 3 IO_L56P_Y Module Table 12: BG432 — XCV300E, XCV400E, XCV600E Pin # Bank Pin Description IO_D5_L58N_YY K2 3 IO_D6_L59P_YY K1 3 IO_VREF_L59N_YY IO_VREF_L60N_Y IO_VREF_L62N_YY IO_VREF_L65N_Y ...
Page 113
... IO_L83N_YY 4 IO_L84P_Y 4 IO_L84N_Y 4 IO_VREF_L85P_Y 4 IO_L85N_Y 4 IO_LVDS_DLL_L86P 5 GCK1 DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 12: BG432 — XCV300E, XCV400E, XCV600E Pin # Bank Pin Description AK4 5 AJ5 5 AH6 5 IO_LVDS_DLL_L86N AL4 5 AK5 5 IO_VREF_L87N_Y AJ6 5 AH7 5 AL5 ...
Page 114
... IO_VREF_L111N_Y 6 IO_L111P_Y 6 IO_VREF_L112N_YY 6 IO_L112P_YY 6 IO_L113N_YY 6 IO_L113P_YY 6 IO_L114N_Y 6 IO_L114P_Y 6 IO_L115N_Y 6 IO_L115P_Y 6 IO_L116N_Y 6 IO_L116P_Y 6 IO_VREF_L117N_YY 6 IO_L117P_YY 6 IO_L118N_Y Module Table 12: BG432 — XCV300E, XCV400E, XCV600E Pin # Bank Pin Description AA30 6 AC30 6 IO_VREF_L119N_Y AD29 6 U31 6 W28 AJ30 7 AH30 7 AG28 7 AH31 7 AG29 7 AG30 7 AF28 7 AG31 7 AF29 ...
Page 115
... VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 12: BG432 — XCV300E, XCV400E, XCV600E Pin # Bank Pin Description G28 NA E31 NA E30 NA F29 NA F28 NA D31 NA D30 NA E29 NA ...
Page 116
... A14 NA A18 NA A23 NA A25 NA A29 NA A30 B30 Notes I/O option only in the XCV600E; otherwise, I/O REF B31 option only I/O option only in the XCV400E, XCV600E; REF C1 otherwise, I/O option only. C31 D16 G1 G31 J1 J31 P1 P31 T4 T28 V1 V31 AC1 AC31 AE1 AE31 www ...
Page 117
R BG432 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also Vir- tex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO ...
Page 118
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 13: BG432 Differential Pin Pair Summary XCV300E, XCV400E, XC600E Pair Bank P N Pin Pin ...
Page 119
... Ball Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless Functions device-dependent as indicated in the footnotes. If the pin is √ VREF not used as V ately following √ - information Table 14: BG560 — XCV400E, XCV600E, XCV1000E XCV1600E, XCV2000E 1 - Bank √ VREF ...
Page 120
... IO_L20P_Y 0 IO_LVDS_DLL_L21N 0 IO_VREF 1 GCK2 IO_LVDS_DLL_L21P 1 IO_VREF_L22N_Y 1 IO_L22P_Y 1 IO_L23N_Y 1 IO_VREF_L23P_Y 1 IO_L24N_Y 1 IO_L24P_Y 1 IO_L25N_Y Module Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank B24 1 E22 1 C23 1 A23 1 D22 1 E21 3 1 B22 1 D21 1 C21 1 B21 1 E20 1 D20 1 C20 1 B20 1 E19 ...
Page 121
... IO_L50N_Y 2 IO_VREF_L51P_YY 2 IO_L51N_YY 2 IO_L52P_Y 2 IO_VREF_L52N_Y 2 IO_L53P_Y 2 IO_L53N_Y 2 IO_VREF_L54P_Y 2 IO_L54N_Y 2 IO_L55P_Y 2 IO_L55N_Y 2 IO_VREF_L56P_YY 2 IO_D1_L56N_YY 2 IO_D2_L57P_YY 2 IO_L57N_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank ...
Page 122
... IO_VREF_L82N_Y 3 IO_L83P_Y 3 IO_L83N_Y 3 IO_L84P_Y 3 IO_VREF_L84N_Y 3 IO_L85P_YY 3 IO_VREF_L85N_YY 3 IO_L86P_Y 3 IO_L86N_Y 3 IO_L87P_Y 3 IO_L87N_Y 3 IO_L88P_Y 3 IO_VREF_L88N_Y 3 IO_L89P_Y 3 IO_L89N_Y 3 IO_L90P_Y Module Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank AA1 Y5 4 AA3 4 AA4 3 4 AB3 4 AA5 4 AC1 4 AB4 4 AC3 4 AB5 4 AC4 ...
Page 123
... IO 5 IO_LVDS_DLL_L115N 5 IO_VREF 5 IO_L116P_Y 5 IO_VREF_L116N_Y 5 IO_L117P_Y 5 IO_L117N_Y 5 IO_L118P_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank AJ12 5 AN11 5 AK12 5 AL12 5 AM12 5 AK13 3 5 AL13 ...
Page 124
... IO_L143P_YY 6 IO_L144N_Y 6 IO_VREF_L144P_Y 6 IO_L145N_Y 6 IO_L145P_Y 6 IO_VREF_L146N_Y 6 IO_L146P_Y 6 IO_L147N_Y 6 IO_L147P_Y 6 IO_VREF_L148N_YY 6 IO_L148P_YY 6 IO_L149N_YY 6 IO_L149P_YY 6 IO_L150N_Y 6 IO_L150P_Y Module Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank AM31 6 AK28 AE33 6 AF31 6 AJ32 6 AL33 6 AH29 6 AJ30 6 AK31 6 AH30 3 6 AG29 6 AJ31 ...
Page 125
... IO_L178P_Y 7 IO_L179N_Y 7 IO_L179P_Y 7 IO_L180N_Y 7 IO_VREF_L180P_Y 7 IO_L181N_Y 7 IO_L181P_Y 7 IO_L182N_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank P32 7 P31 P30 2 P29 3 M32 NA N31 NA N30 NA ...
Page 126
... VCCINT NA VCCINT NA VCCINT 0 VCCO 0 VCCO 0 VCCO 0 VCCO 0 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 2 VCCO 2 VCCO 2 VCCO Module Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pin# See Note Bank N29 2 N33 U30 Y31 3 AB2 3 AB32 4 AD2 4 AD32 4 AG3 4 AG31 4 AJ13 5 AK8 5 ...
Page 127
... REF otherwise, I/O option only. R32 I/O option only in the XCV1000E, 1600E, & 2000E; REF otherwise, I/O option only I/O option only in the XCV600E, 1000E, 1600E, & REF 2000E; otherwise, I/O option only. V33 W2 Y1 Y33 AB1 AC32 AD33 AE2 AG1 ...
Page 128
... A25 E23 11 0 B24 D23 12 0 C23 E22 13 0 D22 A23 14 0 B22 E21 15 0 C21 D21 Module Table 15: BG560 Differential Pin Pair Summary XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Pair Other 23 AO Functions IO_DLL_L15P 26 NA IO_DLL_L15N 27 NA IO_DLL_L21P 28 NA IO_DLL_L21N 29 ...
Page 129
... AA1 AA3 AA4 77 3 AB3 AA5 DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 15: BG560 Differential Pin Pair Summary XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Other AO Functions Pair VREF √ VREF 82 17 VREF VREF 85 19 ...
Page 130
... AN31 AJ27 136 5 AM31 AK28 137 6 AJ30 AH29 138 6 AH30 AK31 139 6 AJ31 AG29 Module Table 15: BG560 Differential Pin Pair Summary XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Other AO Functions Pair √ - 140 √ VREF 141 1 - 142 7 - 143 7 VREF 144 2 VREF 145 ...
Page 131
... AO in the XCV400E, 600E, 1000E, 1600E. 14 the XCV400E, 1000E, 1600E. 15 the XCV600E, 1000E, 2000E. 16 the XCV600E, 2000E. 17 the XCV400E, 600E, 1600E, 2000E. 18 the XCV600E, 1000E, 1600E, 2000E. 19 the XCV400E, 600E, 2000E. 20 the XCV400E, 1000E. DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays ...
Page 132
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Bank Pin Description 1 IO_L11N_Y 1 IO_L11P_Y 1 IO_L12N_YY 1 IO_L12P_YY 1 IO_L13N_YY 1 IO_VREF_L13P_YY 1 IO_L14N_Y 1 IO_L14P_Y 1 IO_L15N_YY 1 IO_VREF_L15P_YY 1 ...
Page 133
R Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Bank Pin Description 4 IO_L43P_Y 4 IO_VREF_L43N_Y 4 IO_L44P_YY 4 IO_L44N_YY 4 IO_VREF_L45P_YY 4 IO_L45N_YY 4 IO_L46P_Y 4 IO_L46N_Y 4 IO_VREF_L47P_YY 4 IO_L47N_YY 4 IO_L48P_YY 4 IO_L48N_YY 4 IO_L49P_Y 4 ...
Page 134
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Bank Pin Description 7 IO_L74N_Y 7 IO_VREF_L74P_Y 7 IO_L75N_YY 7 IO_L75P_YY 7 IO_L76N 7 IO_L76P 7 IO_L77N_YY 7 IO_L77P_YY 7 IO_L78N_Y 7 IO_VREF_L78P_Y 7 ...
Page 135
R Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 136
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 17: FG256 Differential Pin Pair Summary XCV50E, XCV100E, XCV200E, XCV300E P N Pair Bank Pin Pin 19 2 C15 D14 20 2 B16 E13 21 2 C16 E14 22 2 F13 E15 ...
Page 137
R FG456 Fine-Pitch Ball Grid Array Packages XCV200E and XCV300E devices in FG456 fine-pitch Ball Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either in both devices pro- vided in this package. If the pin ...
Page 138
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 18: FG456 — XCV200E and XCV300E Bank Pin Description 1 IO_L23P_Y 1 IO_L24N_YY 1 IO_VREF_L24P_YY 1 IO_L25N_YY 1 IO_L25P_YY 1 IO_L26N_YY 1 IO_VREF_L26P_YY 1 IO_L27N_YY 1 IO_L27P_YY 1 IO_WRITE_L28N_YY 1 IO_CS_L28P_YY 2 ...
Page 139
R Table 18: FG456 — XCV200E and XCV300E Bank Pin Description 3 IO_L50N_YY 3 IO_L51P_YY 3 IO_D5_L51N_YY 3 IO_D6_L52P_Y 3 IO_VREF_L52N_Y 3 IO_L53P_Y 3 IO_L53N_Y 3 IO_L54P_YY 3 IO_L54N_YY 3 IO_L55P_YY 3 IO_VREF_L55N_YY 3 IO_L56P_YY 3 IO_L56N_YY 3 IO_L57P_YY 3 ...
Page 140
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 18: FG456 — XCV200E and XCV300E Bank Pin Description 5 IO_L76N_Y 5 IO_L77P_YY 5 IO_VREF_L77N_YY 5 IO_L78P_YY 5 IO_L78N_YY 5 IO_L79P_Y 5 IO_L79N_Y 5 IO_L80P_Y 5 IO_L80N_Y 5 IO_L81P_YY 5 IO_L81N_YY 5 ...
Page 141
R Table 18: FG456 — XCV200E and XCV300E Bank Pin Description IO_L104N_YY 7 IO_L104P_YY 7 IO_L105N_YY 7 IO_L105P_YY 7 IO_L106N_Y 7 IO_L106P_Y 7 IO_L107N_Y 7 IO_VREF_L107P_Y 7 IO_L108N_YY 7 IO_L108P_YY 7 IO_L109N_YY 7 ...
Page 142
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 18: FG456 — XCV200E and XCV300E Bank Pin Description NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCO_7 NA VCCO_7 NA VCCO_7 NA VCCO_7 NA VCCO_7 NA ...
Page 143
R Table 18: FG456 — XCV200E and XCV300E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 144
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 19: FG456 Differential Pin Pair Summary XCV200E, XCV300E P N Pair Bank Pin Pin 18 1 C14 B14 19 1 A15 F12 20 1 C15 B15 21 1 E14 A16 22 1 ...
Page 145
... DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays FG676 Fine-Pitch Ball Grid Array Package XCV400E and XCV600E devices in the FG676 fine-pitch Ball Grid Array package have footprint compatibility. Pins Other labeled I0_VREF can be used as either in all parts unless ...
Page 146
... IO_L16N_YY 0 IO_L16P_YY 0 IO_VREF_L17N_YY 0 IO_L17P_YY 0 IO_L18N_YY 0 IO_L18P_YY 0 IO_L19N_Y 0 IO_L19P_Y 0 IO_VREF_L20N_Y 0 IO_L20P_Y 0 IO_LVDS_DLL_L21N 1 GCK2 IO_LVDS_DLL_L21P Module Table 20: FG676 — XCV400E, XCV600E Pin # Bank Pin Description G10 1 IO_VREF_L23P_Y C9 1 F10 E10 1 G11 1 D10 1 IO_VREF_L26P_YY B10 1 F11 1 C10 1 E11 1 G12 1 D11 1 C11 1 F12 1 A11 1 E12 ...
Page 147
... IO_L49N_Y 2 IO_L50P_YY 2 IO_L50N_YY 2 IO_VREF_L51P_YY 2 IO_L51N_YY 2 IO_L52P_YY 2 IO_L52N_YY 2 IO_L53P_Y 2 IO_L53N_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Pin # Bank Pin Description D20 2 IO_VREF_L54P_Y F19 2 C21 2 B22 2 E20 2 A23 2 IO_VREF_L56N_YY D21 2 ...
Page 148
... IO_L78P_YY 3 IO_L78N_YY 3 IO_L79P_YY 3 IO_D5_L79N_YY 3 IO_D6_L80P_YY 3 IO_VREF_L80N_YY 3 IO_L81P_YY 3 IO_L81N_YY 3 IO_L82P_Y 3 IO_VREF_L82N_Y 3 IO_L83P_Y 3 IO_L83N_Y 3 IO_L84P_YY 3 IO_L84N_YY 3 IO_L85P_YY Module Table 20: FG676 — XCV400E, XCV600E Pin # Bank Pin Description Y26 3 IO_VREF_L85N_YY AB25 3 1 AC25 3 AC26 3 P21 3 P23 3 P22 3 IO_VREF_L88N_Y R25 3 P19 3 P20 3 R21 3 R22 3 IO_D7_L91P_YY ...
Page 149
... IO_L112P_Y 4 IO_L112N_Y 4 IO_VREF_L113P_Y 4 IO_L113N_Y 4 IO_L114P 4 IO_L114N 4 IO_LVDS_DLL_L115P 5 GCK1 5 IO DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Pin # Bank Pin Description AB19 5 AC20 5 AA18 5 AC19 5 AD20 5 2 AF20 5 AB18 5 AD19 ...
Page 150
... IO_L137N_YY 6 IO_L137P_YY 6 IO_L138N_YY 6 IO_L138P_YY 6 IO_L139N_Y 6 IO_L139P_Y 6 IO_VREF_L140N_Y 6 IO_L140P_Y 6 IO_L141N_Y 6 IO_L141P_Y 6 IO_L142N_YY Module Table 20: FG676 — XCV400E, XCV600E Pin # Bank Pin Description AB9 6 IO_L142P_YY AA9 6 IO_VREF_L143N_YY AF6 6 IO_L143P_YY AC8 6 IO_L144N_YY AC7 6 IO_L144P_YY AD6 AE5 6 IO_VREF_L146N_Y AA8 6 AC6 6 IO_L147N_YY AB8 6 IO_L147P_YY AD5 6 IO_L148N_YY ...
Page 151
... IO_L167P_Y 7 IO_L168N_Y 7 IO_L168P_Y 7 IO_L169N_Y 7 IO_L169P_Y 7 IO_L170N_YY 7 IO_L170P_YY 7 IO_L171N_YY 7 IO_L171P_YY 7 IO_L172N_YY 7 IO_VREF_L172P_YY 7 IO_L173N_YY 7 IO_L173P_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Pin # Bank Pin Description IO_VREF_L174P_Y IO_L176N_YY IO_L176P_YY IO_L177N_YY IO_VREF_L177P_YY ...
Page 152
... Pin Description Module Table 20: FG676 — XCV400E, XCV600E Pin # Bank Pin Description F25 F21 C26 NA C25 B26 NA B24 NA B21 NA B16 NA B11 AF25 NA AF24 NA AF2 NA AE6 NA AE3 NA AE26 NA AE24 NA AE21 NA AE16 NA AE14 NA AE11 NA AE1 NA AD25 NA AD2 NA AD1 NA AA6 AA25 0 AA21 0 AA2 A25 0 www.xilinx.com ...
Page 153
... VCCO 5 VCCO 5 VCCO 6 VCCO 6 VCCO 6 VCCO 6 VCCO 6 VCCO 6 VCCO DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Pin # Bank Pin Description H10 7 J15 7 J14 7 H18 7 H17 7 H16 7 H15 N18 NA M19 ...
Page 154
... M10 NA L17 NA L16 NA L15 NA L14 NA L13 NA L12 NA L11 NA L10 Notes the XCV400E. K17 I/O option only in the XCV600E; otherwise, I/O REF option only. K16 K15 K14 K13 K12 K11 www.xilinx.com 1-800-255-7778 R Pin # GND K10 GND J25 GND J2 GND E5 GND E22 GND ...
Page 155
... F11 B10 15 0 E11 C10 16 0 D11 G12 17 0 F12 C11 DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 21: FG676 Differential Pin Pair Summary XCV400E, XCV600E Pair Other 26 AO Functions IO_DLL_L21N 29 NA IO_DLL_L21P ...
Page 156
... V26 79 3 T20 U23 80 3 V24 U21 81 3 V23 W24 82 3 V22 W26 83 3 Y25 V21 84 3 V20 AA26 85 3 Y24 W23 Module Table 21: FG676 Differential Pin Pair Summary XCV400E, XCV600E Other AO Functions Pair √ VREF 88 √ √ VREF 90 √ √ ...
Page 157
... VREF 174 1 - 175 √ - 176 √ VREF 177 √ - 178 2 - 179 1 VREF 180 √ - 181 √ VREF 182 √ - Notes the XCV600E. √ the XCV400E www.xilinx.com 1-800-255-7778 P N Ban k Pin Pin √ √ √ √ ...
Page 158
... IO_L5N_Y 0 IO_L5P_Y 0 IO_L6N_YY 0 IO_L6P_YY 0 IO_VREF_L7N_YY 0 IO_L7P_YY 0 IO_L8N_Y 0 IO_L8P_Y 0 IO_VREF_L9N_Y 0 IO_L9P_Y 0 IO_L10N_YY 0 IO_L10P_YY 0 IO_VREF_L11N_YY 0 IO_L11P_YY 0 IO_L12N_Y 0 IO_L12P_Y Module Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank and XCV2000E can REF 0 Table 22, see Pin # 0 A20 0 D35 0 B36 0 C35 0 A36 0 1 D34 0 B35 0 C34 0 A35 ...
Page 159
... IO_L43N_Y 1 IO_L43P_Y 1 IO_L44N_YY 1 IO_L44P_YY 1 IO_L45N_YY 1 IO_VREF_L45P_YY 1 IO_L46N_Y 1 IO_L46P_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description C5 1 A19 1 C21 1 IO_L48N_YY 2 B19 1 IO_VREF_L48P_YY C19 1 IO_L49N_YY A18 ...
Page 160
... IO_L71N 2 IO_L72P 2 IO_L72N 2 IO_VREF_L73P_YY 2 IO_L73N_YY 2 IO_L74P_YY 2 IO_L74N_YY 2 IO_L75P 2 IO_L75N 2 IO_VREF_L76P_YY 2 IO_D1_L76N_YY 2 IO_D2_L77P_YY 2 IO_L77N_YY 2 IO_L78P_Y 2 IO_L78N_Y 2 IO_L79P 2 IO_L79N 2 IO_L80P 2 IO_L80N 2 IO_VREF_L81P_Y Module Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description IO_L82P_YY E2 2 IO_L82N_YY IO_VREF_L85P_YY F1 2 IO_D3_L85N_YY J3 2 IO_L86P_YY G2 2 IO_L86N_YY ...
Page 161
... IO_VREF_L111N_YY 3 IO_L112P 3 IO_L112N 3 IO_L113P 3 IO_VREF_L113N 3 IO_L114P_YY 3 IO_L114N_YY 3 IO_L115P_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AA2 3 IO_VREF_L115N_YY AC5 3 IO_L116P_Y AB1 3 IO_L116N_Y AD3 3 AC1 3 AD1 ...
Page 162
... IO_L143P_YY 4 IO_L143N_YY 4 IO_VREF_L144P_YY 4 IO_L144N_YY 4 IO_L145P_Y 4 IO_L145N_Y 4 IO_L146P_Y 4 IO_L146N_Y 4 IO_L147P_YY 4 IO_L147N_YY 4 IO_VREF_L148P_YY 4 IO_L148N_YY 4 IO_L149P_Y 4 IO_L149N_Y Module Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AV8 4 AU9 4 AW8 4 IO_L151P_YY AT10 4 IO_L151N_YY 3 AV9 4 IO_VREF_L152P_YY AU10 4 IO_L152N_YY AW9 4 AT11 4 AV10 4 IO_VREF_L154P AU11 4 AW10 ...
Page 163
... IO_L180P_Y 5 IO_L180N_Y 5 IO_L181P_YY 5 IO_VREF_L181N_YY 5 IO_L182P_YY 5 IO_L182N_YY 5 IO_L183P_Y 5 IO_VREF_L183N_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AV26 5 AW27 5 AU26 AV27 6 AT26 6 AW28 6 AU27 6 IO_L185N_YY AV28 ...
Page 164
... IO_L210N_YY 6 IO_L210P_YY 6 IO_L211N 6 IO_L211P 6 IO_L212N 6 IO_L212P 6 IO_VREF_L213N_YY 6 IO_L213P_YY 6 IO_L214N_YY 6 IO_L214P_YY 6 IO_VREF_L215N 6 IO_L215P Module Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description AH39 7 IO_L216N_YY AG38 7 IO_L216P_YY AG36 7 AG39 7 IO_VREF_L217P AG37 7 IO_L218N_YY AF39 7 IO_L218P_YY AF36 7 IO_L219N_YY AE38 7 IO_VREF_L219P_YY AF37 7 AF38 7 1 AE39 ...
Page 165
... IO_L246P_Y 2 CCLK 3 DONE NA DXN NA DXP PROGRAM NA TCK DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description K38 NA L37 2 J39 NA L36 J38 NA K37 NA H39 NA 3 K36 NA H38 NA ...
Page 166
... VCCO 2 VCCO 3 VCCO 3 VCCO 3 VCCO 3 VCCO 3 VCCO 3 VCCO 4 VCCO 4 VCCO 4 VCCO 4 VCCO 4 VCCO 4 VCCO 5 VCCO 5 VCCO 5 VCCO 5 VCCO 5 VCCO Module Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description 5 E34 6 E33 6 E30 6 E29 6 E27 6 E26 6 E10 7 E11 7 E13 7 E14 AP5 ...
Page 167
... GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Pin # Bank Pin Description D20 NA D12 NA C39 NA C37 C20 B39 NA B38 NA ...
Page 168
... D29 B30 12 0 C29 A30 13 0 B29 A29 14 0 A28 B28 15 0 B27 C28 16 0 A27 D27 17 0 B26 C27 Module Table 23: FG680 Differential Pin Pair Summary XCV600E, XCV1000E, XCV1600E, XCV2000E Pair Other 26 Functions 27 28 IO_DLL_L29N 29 IO_DLL_L29P 30 IO_DLL_L155N 31 IO_DLL_L155P VREF 36 √ ...
Page 169
... DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 23: FG680 Differential Pin Pair Summary XCV600E, XCV1000E, XCV1600E, XCV2000E Other Functions Pair √ VREF 86 √ √ VREF 90 √ VREF √ √ DIN VREF VREF 99 √ - 100 ...
Page 170
... AV16 149 4 AR18 AW16 150 4 AT18 AV17 151 4 AU18 AW17 152 4 AT19 AV18 153 4 AU19 AW18 Module Table 23: FG680 Differential Pin Pair Summary XCV600E, XCV1000E, XCV1600E, XCV2000E Other Functions Pair 4 - 154 4 VREF 155 6 - 156 √ INIT 157 √ - 158 5 - 159 5 VREF 160 √ ...
Page 171
... VREF Notes the XCV1000E, 1600E, 2000E. √ the XCV600E, 1000E, 1600E the XCV600E, 1000E. 4 VREF the XCV1000E, 1600E. √ the XCV1000E, 2000E the XCV600E, 1000E, 2000E. 4 VREF the XCV1000E. √ the XCV2000E. - √ VREF www.xilinx.com 1-800-255-7778 P N Bank Pin ...
Page 172
Virtex™-E 1.8 V Field Programmable Gate Arrays FG860 Fine-Pitch Ball Grid Array Package XCV1000E, XCV1600E, and XCV2000E devices in the FG680 fine-pitch Ball Grid Array package have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts ...
Page 173
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 0 IO_VREF_L27N_YY 0 IO_L27P_YY 0 IO_L28N_Y 0 IO_L28P_Y 0 IO_L29N_Y 0 IO_L29P_Y 0 IO_L30N_YY 0 IO_L30P_YY 0 IO_VREF_L31N_YY 0 IO_L31P_YY 0 IO_L32N_Y 0 IO_L32P_Y 0 IO_VREF_L33N_Y 0 IO_L33P_Y 0 ...
Page 174
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 1 IO_L57N_Y 1 IO_VREF_L57P_Y 1 IO_L58N_Y 1 IO_L58P_Y 1 IO_L59N_YY 1 IO_VREF_L59P_YY 1 IO_L60N_YY 1 IO_L60P_YY 1 IO_L61N_Y 1 IO_L61P_Y 1 IO_L62N_Y 1 ...
Page 175
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 2 IO_D1_L87N_YY 2 IO_D2_L88P_YY 2 IO_L88N_YY 2 IO_L89P_Y 2 IO_L89N_Y 2 IO_L90P_Y 2 IO_L90N_Y 2 IO_L91P_Y 2 IO_L91N_Y 2 IO_L92P 2 IO_L92N 2 IO_L93P_Y 2 IO_L93N_Y 2 IO_VREF_L94P_Y 2 ...
Page 176
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 3 IO_L117N_Y 3 IO_L118P 3 IO_L118N 3 IO_L119P_Y 3 IO_L119N_Y 3 IO_L120P_Y 3 IO_L120N_Y 3 IO_L121P_Y 3 IO_L121N_Y 3 IO_L122P_YY 3 IO_D5_L122N_YY 3 ...
Page 177
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 4 IO_L147N_YY 4 IO_L148P_Y 4 IO_L148N_Y 4 IO_L149P_Y 4 IO_L149N_Y 4 IO_L150P_YY 4 IO_L150N_YY 4 IO_VREF_L151P_YY 4 IO_L151N_YY 4 IO_L152P_Y 4 IO_L152N_Y 4 IO_VREF_L153P_Y 4 IO_L153N_Y 4 IO_L154P_YY 4 ...
Page 178
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 5 IO_L178P_Y 5 IO_L178N_Y 5 IO_L179P_YY 5 IO_VREF_L179N_YY 5 IO_L180P_YY 5 IO_L180N_YY 5 IO_L181P_Y 5 IO_L181N_Y 5 IO_L182P_Y 5 IO_L182N_Y 5 IO_L183P_YY 5 ...
Page 179
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description IO_L211N_YY 6 IO_L211P_YY 6 IO_L212N_Y 6 IO_L212P_Y 6 IO_L213N_Y 6 IO_L213P_Y 6 IO_VREF_L214N_Y 6 IO_L214P_Y 6 ...
Page 180
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 6 IO_VREF_L245N_Y 6 IO_L245P_Y ...
Page 181
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 7 IO_L275N_Y 7 IO_VREF_L275P_Y 7 IO_L276N_Y 7 IO_L276P_Y 7 IO_L277N 7 IO_L277P 7 IO_L278N_Y 7 IO_VREF_L278P_Y 7 IO_L279N_Y 7 IO_L279P_Y 7 IO_L280N_Y 7 IO_L280P_Y 2 CCLK 3 DONE NA ...
Page 182
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA ...
Page 183
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 184
Virtex™-E 1.8 V Field Programmable Gate Arrays FG860 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the ...
Page 185
R Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin 52 1 D11 B15 53 1 C14 E11 54 1 B14 C10 55 1 E10 A13 C13 57 1 A12 ...
Page 186
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin 120 3 AH1 AL5 121 3 AH2 AM4 122 3 AH3 AM5 123 3 AJ1 AN3 124 ...
Page 187
R Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin 188 5 AY27 AV28 189 5 BA27 AW29 190 5 BB28 AV29 191 5 AY28 AW30 192 5 BA28 AW31 193 5 BB29 ...
Page 188
... FG900 fine-pitch Ball Grid Array package have footprint compatibility. Pins labeled I0_VREF can be used as either AO Functions in all parts unless device-dependent as indicated in the foot- √ - notes. If the pin is not used as V eral I/O. Immediately following 1 VREF Differential Pair information Table 26: FG900 — XCV600E, XCV1000E, XCV1600E 4 - Bank √ ...
Page 189
... IO_L20N_Y 0 IO_L20P_Y 0 IO_L21N_Y 0 IO_L21P_Y 0 IO_L22N_YY 0 IO_L22P_YY 0 IO_VREF_L23N_YY 0 IO_L23P_YY 0 IO_L24N_Y DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description N11 0 IO_L26N_YY G9 0 IO_L26P_YY E8 0 IO_VREF_L27N_YY A6 0 IO_L27P_YY ...
Page 190
... IO_L45N_YY 1 IO_VREF_L45P_YY 1 IO_L46N_YY 1 IO_L46P_YY 1 IO_L47N_Y 1 IO_L47P_Y 1 IO_L48N_Y 1 IO_L48P_Y 1 IO_L49N_Y 1 IO_L49P_Y 1 IO_L50N_YY 1 IO_L50P_YY 1 IO_L51N_YY 1 IO_L51P_YY Module 104 Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description 5 J20 1 IO_L52N_YY 4 L18 1 IO_VREF_L52P_YY E16 1 IO_L53N_YY B16 1 IO_L53P_YY 2 F16 1 IO_L54N_YY A16 1 IO_L54P_YY H16 1 IO_L55N_YY C16 ...
Page 191
... IO_VREF_L76P_Y 2 IO_L76N_Y 2 IO_L77P_YY 2 IO_L77N_YY 2 IO_L78P_YY 2 IO_L78N_YY 2 IO_L79P 2 IO_L79N 2 IO_VREF_L80P_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description 5 D29 2 IO_L80N_YY 4 G26 2 IO_L81P_YY 4 H24 2 IO_L81N_YY 4 H25 2 5 H28 ...
Page 192
... IO_L106N 3 IO_L107P_YY 3 IO_VREF_L107N_YY 3 IO_L108P_YY Module 106 Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description N26 3 IO_L108N_YY P28 3 IO_L109P_YY P29 3 IO_VREF_L109N_YY N24 3 IO_L110P_YY P22 3 IO_L110N_YY R26 3 P25 3 R29 3 IO_L112P_YY 4 R21 3 IO_L112N_YY 3 R28 3 IO_D4_L113P_YY 2 R25 3 IO_VREF_L113N_YY T30 3 4 P24 3 3 R27 ...
Page 193
... IO_L139N 3 IO_L140P 3 IO_L140N 3 IO_D7_L141P_YY 3 IO_INIT_L141N_YY 4 GCK0 DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description Y24 4 AB28 4 AC30 4 AA25 4 W21 4 AA24 4 AB26 4 AD30 4 Y22 4 AC27 4 AD28 ...
Page 194
... IO_L166N_YY 4 IO_L167P 4 IO_L167N 4 IO_L168P 4 IO_L168N 4 IO_L169P_YY 4 IO_L169N_YY 4 IO_VREF_L170P_YY 4 IO_L170N_YY 4 IO_L171P 4 IO_L171N 4 IO_L172P 4 IO_L172N Module 108 Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description AG23 4 IO_L173P_YY AF22 4 IO_L173N_YY AE22 4 IO_VREF_L174P_YY AJ22 4 IO_L174N_YY AG22 4 4 AK24 4 3 AD20 4 IO_VREF_L176P_YY AA19 4 IO_L176N_YY ...
Page 195
... IO_L197P_YY 5 IO_L197N_YY 5 IO_L198P_YY 5 IO_VREF_L198N_YY 5 IO_L199P_YY 5 IO_L199N_YY 5 IO_L200P 5 IO_L200N DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description AF13 5 AH14 5 AJ14 5 IO_L202P_YY AE14 5 IO_VREF_L202N_YY AG13 5 IO_L203P_YY AK13 ...
Page 196
... IO_L221P 6 IO_VREF_L222N_YY 6 IO_L222P_YY 6 IO_L223N_YY 6 IO_L223P_YY 6 IO_L224N 6 IO_L224P 6 IO_L225N_YY 6 IO_L225P_YY 6 IO_VREF_L226N_YY 6 IO_L226P_YY 6 IO_L227N_YY 6 IO_L227P_YY 6 IO_L228N_YY 6 IO_L228P_YY Module 110 Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description 4 AC5 6 IO_L229N_YY 4 AD1 6 IO_VREF_L229P_YY 5 AE5 6 AF3 6 AC6 6 IO_L231N_YY 4 AH2 6 IO_L231P_YY 3 AG2 6 AB9 6 AE4 6 IO_L233N_YY ...
Page 197
... IO_L250P_YY 7 IO_L251N_YY 7 IO_VREF_L251P_YY 7 IO_L252N_YY 7 IO_L252P_YY 7 IO_L253N 7 IO_L253P 7 IO_L254N_YY 7 IO_L254P_YY 7 IO_L255N_YY 7 IO_VREF_L255P_YY 7 IO_L256N DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description IO_L257N_YY IO_L257P_YY IO_L258N_YY IO_L258P_YY IO_VREF_L259P ...
Page 198
... IO_L280N_YY 7 IO_VREF_L280P_YY 7 IO_L281N 7 IO_L281P 7 IO_L282N_YY 7 IO_L282P_YY 2 CCLK 3 DONE NA DXN NA DXP PROGRAM NA TCK NA TDI 2 TDO NA TMS NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT Module 112 Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description K10 NA NA F26 NA AJ28 NA AJ3 NA AH4 NA AF4 ...
Page 199
... VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_5 DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Pin # Bank Pin Description C12 NA B25 NA C19 NA M18 NA M17 NA L17 NA H17 NA L16 NA ...
Page 200
... Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND ...