XCV600E-6BGG432C Xilinx Inc, XCV600E-6BGG432C Datasheet - Page 71

• Manufacturer Part Number: XCV600E-6BGG432C
• Description: FPGA Virtex-E Family 186.624K Gates 15552 Cells 357MHz 0.18um (CMOS) Technology 1.8V 432-Pin BGA
• Manufacturer: Xilinx Inc

Specifications of XCV600E-6BGG432C

• Package: 432BGA
• Family Name: Virtex-E
• Device Logic Gates: 186624
• Device Logic Units: 15552
• Device System Gates: 985882
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 316
• Ram Bits: 294912
• Re-programmability Support: Yes

Calculation of T
T
the pad. The values for T
capacitive load (C
Table
Table 3: Constants for Use in Calculation of T
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
Notes:
1.
2.
LVTTL Fast Slew Rate, 2mA drive
LVTTL Fast Slew Rate, 4mA drive
LVTTL Fast Slew Rate, 6mA drive
LVTTL Fast Slew Rate, 8mA drive
LVTTL Fast Slew Rate, 12mA drive
LVTTL Fast Slew Rate, 16mA drive
LVTTL Fast Slew Rate, 24mA drive
LVTTL Slow Slew Rate, 2mA drive
LVTTL Slow Slew Rate, 4mA drive
LVTTL Slow Slew Rate, 6mA drive
LVTTL Slow Slew Rate, 8mA drive
LVTTL Slow Slew Rate, 12mA drive
LVTTL Slow Slew Rate, 16mA drive
LVTTL Slow Slew Rate, 24mA drive
LVCMOS2
LVCMOS18
PCI 33 MHZ 3.3 V
PCI 66 MHz 3.3 V
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
CTT
AGP
ioop
I/O parameter measurements are made with the capacitance
values shown above. See the application examples (in
Module 2 of this data sheet) for appropriate terminations.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
is the propagation delay from the O Input of the IOB to
3.
R
Standard
sl
ioop
) for each I/O standard as listed in
as a Function of Capacitance
ioop
are based on the standard
Csl (pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
20
20
20
30
30
30
30
20
10
0
0
fl (ns/pF)
ioop
0.079
0.044
0.043
0.033
0.086
0.058
0.050
0.048
0.041
0.050
0.050
0.033
0.014
0.017
0.022
0.016
0.014
0.028
0.016
0.029
0.016
0.035
0.037
0.41
0.20
0.13
0.41
0.20
0.10
www.xilinx.com
1-800-255-7778
For other capacitive loads, use the formulas below to calcu-
late the corresponding T
where:
Table 4: Delay Measurement Methodology
Notes:
1.
2.
LVTTL
LVCMOS2
PCI33_3
PCI66_3
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 I & II
SSTL2 I & II
CTT
AGP
LVDS
LVPECL
Standard
T
T
Adjustment section.
C
Input waveform switches between V
Measurements are made at V
Minimum. Worst-case values are reported.
I/O parameter measurements are made with the
capacitance values shown in
examples (in Module 2 of this data sheet) for appropriate
terminations.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
opadjust
ioop
load
Virtex™-E 1.8 V Field Programmable Gate Arrays
= T
is the capacitive load for the design.
is reported above in the Output Delay
ioop
V
+ T
(0.2xV
1.2
V
V
V
V
V
V
V
REF
1.6
REF
REF
REF
REF
REF
REF
REF
V
opadjust
REF
V
–
0
0
L
0.125
–
–
–
–0.2
–
–
–
–
–
1
CCO
0.3
0.75
0.2
0.2
0.5
0.5
0.5
1.0
–
ioop
)
Per PCI Spec
Per PCI Spec
+ (C
:
V
(0.2xV
1.2 + 0.125
V
V
V
V
V
V
V
1.6 + 0.3
REF
Table
REF
REF
REF
REF
REF
REF
REF
V
REF
load
REF
V
2.5
3
H
+0.75
+0.2
+0.2
+0.5
+0.5
+0.5
+1.0
+0.2
(Typ), Maximum, and
1
CCO
– C
3. See the application
+
L
and V
)
sl
) * fl
Meas.
1.125
Point
H
V
V
V
V
V
V
V
V
V
1.4
1.2
1.6
.
REF
REF
REF
REF
REF
REF
REF
REF
REF
Module 3 of 4
(Typ)
V
Spec
AGP
0.80
0.75
0.90
0.90
1.25
Per
1.0
1.5
1.5
REF
-
-
-
-
2
11