XCV600E-6BGG432C Xilinx Inc, XCV600E-6BGG432C Datasheet - Page 97

• Manufacturer Part Number: XCV600E-6BGG432C
• Description: FPGA Virtex-E Family 186.624K Gates 15552 Cells 357MHz 0.18um (CMOS) Technology 1.8V 432-Pin BGA
• Manufacturer: Xilinx Inc

Specifications of XCV600E-6BGG432C

• Package: 432BGA
• Family Name: Virtex-E
• Device Logic Gates: 186624
• Device Logic Units: 15552
• Device System Gates: 985882
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 316
• Ram Bits: 294912
• Re-programmability Support: Yes

PQ240 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
.
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Pair
10
11
12
13
14
15
0
1
2
3
0
1
2
3
4
5
6
7
8
9
Total Pairs: 64, Asynchronous Outputs Pairs: 27
Bank
4
5
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
2
R
P Pin
Global Differential Clock
P210
P213
P236
P234
P228
P223
P220
P217
P209
P205
P202
P199
P194
P191
P188
P186
P184
P178
P92
P89
IO LVDS
N Pin
P209
P215
P237
P235
P229
P224
P221
P218
P215
P206
P203
P200
P195
P192
P189
P187
P185
P177
P93
P87
AO
NA
NA
NA
NA
NA
1
3
3
3
3
1
√
√
√
√
√
√
√
√
√
IO_LVDS_DLL
IO_DLL_L40P
IO_DLL_L40N
IO_DLL_L6N
IO_DLL_L6P
Functions
DIN, D0
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
CS
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
Pair
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Virtex™-E 1.8 V Field Programmable Gate Arrays
Bank
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
P Pin
P174
P171
P168
P163
P160
P157
P155
P153
P145
P142
P139
P134
P131
P128
P126
P124
P118
P114
P111
P108
P103
P100
P97
P95
P93
P84
P79
P74
P71
P68
P66
P64
N Pin
P173
P170
P167
P162
P159
P156
P154
P152
P144
P141
P138
P133
P130
P127
P125
P123
P117
P113
P110
P107
P102
P99
P96
P94
P87
P82
P78
P73
P70
P67
P65
P63
AO
NA
2
3
4
√
2
4
5
√
4
2
√
4
3
2
6
√
√
√
√
√
√
3
3
7
8
√
√
√
√
1
√
IO_LVDS_DLL
Functions
D1, VREF
D3, VREF
D4, VREF
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
Module 4 of 4
INIT
D2
D5
-
-
-
-
-
-
-
-
-
-
-
-
11