XCV600E-6BGG432C Xilinx Inc, XCV600E-6BGG432C Datasheet - Page 93

• Manufacturer Part Number: XCV600E-6BGG432C
• Description: FPGA Virtex-E Family 186.624K Gates 15552 Cells 357MHz 0.18um (CMOS) Technology 1.8V 432-Pin BGA
• Manufacturer: Xilinx Inc

Specifications of XCV600E-6BGG432C

• Package: 432BGA
• Family Name: Virtex-E
• Device Logic Gates: 186624
• Device Logic Units: 15552
• Device System Gates: 985882
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 316
• Ram Bits: 294912
• Re-programmability Support: Yes

Table 5: CS144 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E
PQ240 Plastic Quad Flat-Pack Packages
XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in PQ240 Plastic Flat-pack packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as V
eral I/O. Immediately following
Differential Pair information.
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Pair
18
19
20
21
22
23
24
25
26
27
28
29
P236
P229
Note 1: AO in the XCV50E
Pin #
P238
P237
P235
P234
P231
P230
P228
P224
P223
Bank
2
1
5
5
5
5
6
6
6
6
7
7
7
7
R
Pin
N8
N3
H3
H1
D2
K6
K5
K3
F2
E1
E3
J2
P
IO_VREF_L2N_YY
IO_VREF_L0P_Y
Pin Description
IO_L1N_YY
IO_L3N_YY
IO_L1P_YY
IO_L2P_YY
IO_L3P_YY
IO_L0N_Y
IO_VREF
Pin
M6
M3
G1
N5
N4
H4
H2
F4
E2
D1
L1
J3
N
IO
IO
REF
Table
AO
, it can be used as gen-
NA
NA
√
√
√
√
1
√
1
1
√
1
6, see
IO_LVDS_DLL
Functions
Other
VREF
VREF
VREF
VREF
VREF
Table 7
-
-
-
-
-
-
Bank
0
0
0
0
0
0
0
0
0
0
0
www.xilinx.com
1-800-255-7778
for
Table 6: PQ240 — XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E
P216
P208
P194
P187
P175
Pin #
P222
P221
P220
P218
P217
P215
P213
P210
P209
P206
P205
P203
P202
P201
P200
P199
P195
P193
P192
P191
P189
P188
P186
P185
P184
P178
P177
P174
Virtex™-E 1.8 V Field Programmable Gate Arrays
3
3
1
2
2
IO_DOUT_BUSY_L15P_YY
IO_DIN_D0_L15N_YY
IO_WRITE_L14N_YY
IO_VREF_L10P_YY
IO_VREF_L11P_YY
IO_LVDS_DLL_L6N
IO_LVDS_DLL_L6P
IO_VREF_L13N_Y
IO_VREF_L5N_Y
IO_VREF_L7P_Y
IO_CS_L14P_YY
Pin Description
IO_L10N_YY
IO_L11N_YY
IO_L12N_YY
IO_L12P_YY
IO_L9N_YY
IO_L9P_YY
IO_L13P_Y
IO_L16P_Y
IO_L4N_Y
IO_L4P_Y
IO_L5P_Y
IO_L7N_Y
IO_L8N_Y
IO_L8P_Y
IO_VREF
IO_VREF
IO_VREF
GCK3
GCK2
IO
IO
IO
Module 4 of 4
Bank
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
7