XCV600E-6BGG432C Xilinx Inc, XCV600E-6BGG432C Datasheet - Page 119

• Manufacturer Part Number: XCV600E-6BGG432C
• Description: FPGA Virtex-E Family 186.624K Gates 15552 Cells 357MHz 0.18um (CMOS) Technology 1.8V 432-Pin BGA
• Manufacturer: Xilinx Inc

Specifications of XCV600E-6BGG432C

• Package: 432BGA
• Family Name: Virtex-E
• Device Logic Gates: 186624
• Device Logic Units: 15552
• Device System Gates: 985882
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 316
• Ram Bits: 294912
• Re-programmability Support: Yes

Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Notes:
1.
2.
3.
4.
5.
Pair
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
AO in the XCV300E, 600E.
AO in the XCV300E.
AO in the XCV400E, 600E.
AO in the XCV300E, 400E.
AO in the XCV600E.
Bank
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
R
AB29
AA29
W30
M28
U29
U30
R29
R31
N30
N31
G30
G28
D30
Y29
Y31
V29
P28
L30
K30
F31
E30
F28
E28
J30
J28
Pin
P
AB28
AB31
W29
M29
M30
G29
Y28
Y30
V28
V30
U28
R30
P29
P30
N28
K31
K28
H30
H28
E31
D31
E29
T31
F29
J29
Pin
N
AO
√
√
4
1
1
√
4
1
√
1
4
√
1
1
4
√
√
1
4
√
1
5
1
4
3
Functions
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
Other
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
BG560 Ball Grid Array Packages
XCV1000E, XCV1600E, and XCV2000E devices in BG560
Ball Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V
ately following
information.
Table 14: BG560 — XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Virtex™-E 1.8 V Field Programmable Gate Arrays
IO_VREF_L10N_YY
IO_VREF_L2N_YY
IO_VREF_L5N_YY
IO_VREF_L8N_Y
IO_VREF_L6P_Y
REF
Pin Description
IO_VREF_L0P
Table
IO_L11N_YY
IO_L10P_YY
IO_L1N_YY
IO_L1P_YY
IO_L2P_YY
IO_L4N_YY
IO_L4P_YY
IO_L5P_YY
IO_L3N_Y
IO_L6N_Y
IO_L7N_Y
IO_L9N_Y
IO_L3P_Y
IO_L7P_Y
IO_L8P_Y
IO_L9P_Y
, it can be used as general I/O. Immedi-
IO_L0N
GCK3
14, see
IO
IO
IO
IO
IO
Table 15
for Differential Pair
Pin#
C28
C30
D30
D29
D28
C29
D27
D26
C27
D25
C26
C25
D24
D23
A17
A27
B25
E28
A31
E27
B30
E26
B29
E25
A28
E24
B26
E23
A25
Module 4 of 4
See Note
3
1
4
33