AT89LP828 Atmel Corporation, AT89LP828 Datasheet - Page 102

• Manufacturer Part Number: AT89LP828
• Manufacturer: Atmel Corporation

Specifications of AT89LP828

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 1024
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 18-1.
Notes:
102
Symbol
CSA
[1 - 0]
CONA
CFA
CENA
CMA
[2 - 0]
ACSRA = 97H
Not Bit Addressable
Bit
1. CONA must be cleared to 0 before changing CSA [1 - 0].
2. Debouncing modes require the use of Timer 1 to generate the sampling delay.
AT89LP428/828
Function
Comparator A Positive Input Channel Select
Comparator A Input Connect. When CONA = 1 the analog input pins are connected to the comparator. When CONA = 0
the analog input pins are disconnected from the comparator. CONA must be cleared to 0 before changing CSA [1 - 0] or
RFA [1 - 0].
Comparator A Interrupt Flag. Set when the comparator output meets the conditions specified by the CMA [2 - 0] bits and
CENA is set. The flag must be cleared by software. The interrupt may be enabled/disabled by setting/clearing bit 6 of IE.
Comparator A Enable. Set this bit to enable the comparator. Clearing this bit will force the comparator output low and
prevent further events from setting CFA. When CENA = 1 the analog input pins, P2.4 - P2.7, have their digital inputs
disabled if they are configured in input-only mode.
Comparator Interrupt Mode
CMA2
CSA1
ACSRA
CSA1
0
0
1
1
0
0
0
0
1
1
1
1
7
– Analog Comparator a Control and Status Register
CMA1
CSA0
0
1
0
1
0
0
1
1
0
0
1
1
CSA0
6
A+ Channel
AIN0 (P2.4)
AIN1 (P2.5)
AIN2 (P2.6)
AIN3 (P2.7)
CMA0
0
1
0
1
0
1
0
1
CONA
5
Interrupt Mode
Negative (Low) level
Positive edge
Toggle with debouncing
Positive edge with debouncing
Negative edge
Toggle
Negative edge with debouncing
Positive (High) level
(1)
CFA
4
(2)
CENA
3
(2)
(2)
CMA2
2
Reset Value = 0000 0000B
CMA1
1
CMA0
3654A–MICRO–8/09
0