AT89LP828 Atmel Corporation, AT89LP828 Datasheet - Page 14

• Manufacturer Part Number: AT89LP828
• Manufacturer: Atmel Corporation

Specifications of AT89LP828

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 1024
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 3-4.
3.4
14
Symbol
IAP
AERS
LDPG
MWEN
DMEN
ABORT
WRTINH
MEMCON = 96H
Not Bit Addressable
Bit
In-Application Programming (IAP)
AT89LP428/828
Function
In-Application Programming Enable. When IAP = 1 and the IAP Fuse is enabled, programming of the CODE/SIG space
is enabled and MOVX @DPTR instructions will access CODE/SIG instead of EDATA or FDATA. Clear IAP to disable
programming of CODE/SIG and allow access to EDATA and FDATA.
Auto-Erase Enable. Set to perform an auto-erase of a Flash memory page (CODE, SIG or FDATA) during the next write
sequence. Clear to perform write without erase.
Load Page Enable. Set to this bit to load multiple bytes to the temporary page buffer. Byte locations may not be loaded
more than once before a write. LDPG must be cleared before writing.
Memory Write Enable. Set to enable programming of a nonvolatile memory location (CODE, SIG or FDATA). Clear to
disable programming of all nonvolatile memories.
Data Memory Enable. Set to enable nonvolatile data memory and map it into the FDATA space. Clear to disable
nonvolatile data memory.
Abort Flag. Set by hardware if an error occurred during the last programming sequence due to a brownout condition
(low voltage on V
Write Inhibit Flag.
voltage. Set by hardware when the voltage on V
MEMCON
IAP
7
– Memory Control Register
The AT89LP428/828 supports In-Application Programming (IAP), allowing the program memory
to be modified during execution. The IAP can be used to modify the user application on-the-fly or
to use program memory for nonvolatile data storage. The same write protocol for FDATA also
applies to IAP (see
ing the program memory. When the write completes, the CPU will continue executing with the
instruction after the MOVX @DPTR,A instruction that started the write.
To enable access to the program memory, the IAP bit (MEMCON.7) must be set to one and the
IAP User Fuse must be enabled. The IAP User Fuse can disable all IAP operations. When this
fuse is disabled, the IAP bit will be forced to 0. While IAP is enabled, all MOVX @DPTR instruc-
tions will access the CODE space instead of EDATA or FDATA. The IAP also allows
reprogramming of the User Signature Array when SIGEN = 1. The IAP access settings are sum-
marized in
Table 3-5.
AERS
CC
Cleared by hardware when the voltage on V
). Must be cleared by software.
6
IAP
0
0
0
0
1
1
Table
IAP Access Settings
LDPG
SIGEN
3-5.
5
0
0
1
1
0
1
“Write Protocol” on page
MWEN
DMEN
4
X
X
0
1
0
1
CC
is above the minimum programming voltage.
DMEN
3
12). The CPU is always placed in idle while modify-
MOVX @DPTR
CC
EDATA
EDATA
FDATA
FDATA
CODE
has fallen below the minimum programming
SIG
ABORT
2
Reset Value = 0000 00XXB
–
1
MOVC @DPTR
CODE
CODE
CODE
WRTINH
SIG
SIG
SIG
3654A–MICRO–8/09
0