AT89LP828 Atmel Corporation, AT89LP828 Datasheet - Page 8

• Manufacturer Part Number: AT89LP828
• Manufacturer: Atmel Corporation

Specifications of AT89LP828

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 1024
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

2.2.6
2.2.7
2.2.8
3. Memory Organization
8
AT89LP428/828
Serial Port
Watchdog Timer
I/O Ports
The baud rate of the UART in Mode 0 defaults to 1/4 the clock frequency, compared to 1/12 the
clock frequency in the standard 8051. In should also be noted that when using Timer 1 to gener-
ate the baud rate in UART Modes 1 or 3, the timer counts at the clock frequency and not at 1/12
the clock frequency. To maintain the same baud rate in the AT89LP428/828 while running at the
same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of
Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud
rates. Timer 2 generated baud rates are twice as fast in the AT89LP428/828 than on standard
8051s when operating at the same frequency.
The Watchdog Timer in AT89LP428/828 counts at a rate of once per clock cycle. This compares
to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time
base for all timers and reduce the counting rate.
The I/O ports of the AT89LP428/828 may be configured in four different modes. By default all
the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all
ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must
be put into quasi-bidirectional mode by clearing the P1M0, P2M0, P3M0 and P4M0 SFRs. The
user can also configure the ports to start in quasi-bidirectional mode by disabling the Tristate-
Port User Fuse. When this fuse is disabled, P1M0, P2M0, P3M0 and P4M0 will reset to 00H
instead of FFH and the ports will be weakly pulled high.
The AT89LP428/828 uses a Harvard Architecture with separate address spaces for program
and data memory. The program memory has a regular linear address space with support for
up to 64K bytes of directly addressable application code. The data memory has 256 bytes of
internal RAM and 128 bytes of Special Function Register I/O space. The AT89LP428/828
does not support external data memory or external program memory; however, portions of the
external data memory space are implemented on chip as Extra RAM and nonvolatile Flash
data memory. The memory address spaces of the AT89LP428 and AT89LP828 are listed in
Tables 3-1 and
Table 3-1.
Name
DATA
IDATA
SFR
EDATA
FDATA
CODE
SIG
AT89LP428 Memory Address Spaces
3-2.
Description
Directly addressable internal RAM
Indirectly addressable internal RAM and stack space
Directly addressable I/O register space
On-chip Extra RAM
On-chip nonvolatile Flash data memory
On-chip nonvolatile Flash program memory
On-chip nonvolatile Flash signature array
0000H - 0FFFH
0000H - 01FFH
0200H - 03FFH
0000H - 00FFH
00H - FFH
80H - FFH
00H - 7FH
3654A–MICRO–8/09
Range