AT89LP828 Atmel Corporation, AT89LP828 Datasheet - Page 20

• Manufacturer Part Number: AT89LP828
• Manufacturer: Atmel Corporation

Specifications of AT89LP828

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 1024
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

5.2
5.2.1
5.2.2
6. System Clock
20
Restrictions on Certain Instructions
AT89LP428/828
Branching Instructions
MOVX-related Instructions
The AT89LP428/828 is an economical and cost-effective member of Atmel's growing family of
microcontrollers. It contains 4K/8K bytes of Flash program memory. It is fully compatible with the
MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However,
there are a few considerations one must keep in mind when utilizing certain instructions to pro-
gram this device. All the instructions related to jumping or branching should be restricted such
that the destination address falls within the physical program memory space of the device, which
is 0000H–0FFFH for the AT89LP428 and 0000H–1FFFH for the AT89LP828. This should be the
responsibility of the software programmer. For example, LJMP 07E0H would be a valid instruc-
tion, whereas LJMP 9000H would not. A typical 8051 assembler will still assemble instructions,
even if they are written in violation of the restrictions mentioned above. It is the responsibility of
the user to know the physical features and limitations of the device being used and to adjust the
instructions used accordingly.
The LCALL, LJMP, ACALL, AJMP, SJMP, and JMP @A+DPTR unconditional branching instruc-
tions will execute correctly as long as the programmer keeps in mind that the destination
branching address must fall within the physical boundaries of the program memory size. Violat-
ing the physical space limits may cause unknown program behavior. With the CJNE [...], DJNZ
[...], JB, JNB, JC, JNC, JBC, JZ, and JNZ conditional branching instructions, the same previous
rule applies. Again, violating the memory boundaries may cause erratic execution.
The AT89LP428/828 contains 512 bytes of internal Extra RAM and 512/1024 bytes of Flash
data memory mapped into the XRAM address space. MOVX accesses to addresses above
03FFH/05FFH will return invalid data.
The system clock is generated directly from one of three selectable clock sources. The three
sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The
on-chip crystal oscillator may also be configured for low and high speed operation. The clock
source is selected by the Clock Source User Fuses as shown in
tion Fuses” on page 121.
from the system clock. However, the system clock divider may be used to prescale the system
clock. The choice of clock source also affects the start-up time after a POR, BOD or Power-
down event (see
Table 6-1.
Clock Source
Fuse 1
0
0
1
1
Clock Source Settings
“Reset” on page 23
By default, no internal clock division is used to generate the CPU clock
Clock Source
Fuse 0
0
1
0
1
or
“Power-down Mode” on page
Selected Clock Source
High Speed Crystal Oscillator (f > 500 kHz)
Low Speed Crystal Oscillator (f ≤ 100 kHz)
External Clock on XTAL1
Internal 8 MHz RC Oscillator
Table
27).
6-1.
See “User Configura-
3654A–MICRO–8/09