ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 192

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.3.2
17.3.3
8077H–AVR–12/09
STATUS - Real Time Counter Status Register
INTCTRL - Real Time Counter Interrupt Control Register
• Bits 7:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - SYNCBUSY: RTC Synchronization Busy Flag
This bit is set when the CNT, CTRL, PER or COMP register is busy synchronizing between the
RTC clock and system clock domains.
• Bits 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 3:2 - COMPINTLVL[1:0]: RTC Compare Match Interrupt Enable
These bits enable the RTC Compare Match Interrupt and select the interrupt level as described
in
enabled interrupt will trigger when the COMPIF in the INTFLAGS register is set.
• Bits 1:0 - OVFINTLVL[1:0]: RTC Overflow Interrupt Enable
These bits enable the RTC Overflow Interrupt and select the interrupt level as described in
tion 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
interrupt will trigger when the OVFIF in the INTFLAGS register is set.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
7
R
0
-
7
R
0
-
R
6
0
-
6
R
0
-
R
5
0
-
R
5
0
-
R
4
0
-
R
4
0
-
R/W
R
3
0
COMPINTLVL[1:0]
-
3
0
R/W
R
2
0
-
2
0
R
R/W
1
0
-
1
OVFINTLVL[1:0]
0
XMEGA A
SYNCBUSY
123. The enabled
R/W
R/W
0
0
0
0
123. The
INTCTRL
STATUS
Sec-
192