ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 299

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.9.5
25.9.6
8077H–AVR–12/09
Single conversions on two ADC channels, CH1 with gain
Free running mode on two ADC channels with gain
Figure 25-16. ADC timing for single conversion on two ADC channels, CH0 with gain
Figure 25-17 on page 299
nels where ADC Channel 1 uses the gain stage.
Figure 25-17. ADC timing for single conversion on two ADC channels, CH1 with gain
Figure 25-18 on page 300
mode, CH0 and CH1 without gain and CH2 and CH3 with gain. When set up in free running
mode a ADC channel will continuously sample and do new conversions. In this example all ADC
channels are triggered at the same time, and each ADC channel sample and start converting as
soon as the previous ADC channel is done with it sample and MSB conversion. After four ADC
clock cycles all ADC channels have done the first sample and started the first conversion, and
each ADC channels can then do the sample conversion start for the second conversions. After 8
(for 12-bit mode) ADC clock cycles the first conversion is done for ADC Channel 0, and the
results for the rest of the ADC Channels is available in the next ADC clock cycles. After the next
clock cycle (in cycle 10) the result from the second ADC Channel is done and available and so
on. In this mode up to 8 conversions are ongoing at the same time.
CONVERTING BIT CH0
CONVERTING BIT CH1
CONVERTING BIT CH0
CONVERTING BIT CH1
GAINSTAGE AMPLIFY
GAINSTAGE AMPLIFY
GAINSTAGE SAMPLE
GAINSTAGE SAMPLE
START CH1, wo/GAIN
START CH0, wo/GAIN
START CH0, w/GAIN
START CH1, w/GAIN
ADC SAMPLE
ADC SAMPLE
CLK
CLK
IF CH0
IF CH1
IF CH0
IF CH1
ADC
ADC
1
1
shows the conversion timing for single conversions on two ADC chan-
shows the conversion timing for all four ADC channels in free running
2
2
MSB
MSB
10
10
3
3
MSB
MSB
9
9
10
10
8
8
4
4
7
9
7
9
6
8
6
8
5
5
5
7
5
7
4
6
4
6
6
6
3
5
3
5
2
4
2
4
7
7
1
3
1
3
LSB
LSB
2
2
8
8
1
1
XMEGA A
LSB
LSB
9
9
10
10
299