ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 268

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24. EBI - External Bus Interface
24.1
24.2
24.3
24.3.1
8077H–AVR–12/09
Features
Overview
Chip Select
Base Address
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The External Bus Interface (EBI) is the interface for connecting external peripheral and memory
to access it through the data memory space. When the EBI is enabled, data address space out-
side the internal SRAM becomes available using dedicated EBI pins.
The EBI can interface external SRAM, SDRAM, and/or peripherals such as LCD displays and
other memory mapped devices.
The address space, and the number of pins used for the external memory is selectable from 256
bytes (8-bit) and up to 16M bytes (24-bit). Various multiplexing modes for address and data lines
can be selected for optimal use of pins when more or less pins are available for the EBI. The
complete memory will be mapped into one linear data address space continuing from the end of
the internal SRAM, refer to
The EBI has four chip selects with separate configuration. Each can be configured for SRAM,
SRAM Low Pin Count (LPC) or SDRAM.
The EBI is clocked from the Fast Peripheral clock, running up to two times faster than the CPU
and supporting speeds of up to 64 MHz.
For SDRAM both 4-bit and 8-bit SDRAM is supported, and SDRAM configurations such as CAS
Latency and Refresh rate is configurable in software.
For more details on SRAM and SDRAM, and how these memory types are organized and work,
refer to SRAM and SDRAM specific documentation and data sheets. This section only contains
EBI specific details.
The EBI module has four Chip Select lines (CS0 to CS3) where each can be associated with
separate address ranges. The chip selects control which memory or memory mapped external
hardware that is accessed when a given memory address is issued on the EBI. Each Chip
Select has separate configuration, and can be configured for SRAM or SRAM Low Pin Count
(LPC). Chip Select 3 can also be configured for SDRAM.
The data memory address space associated for each chip select is decided by a configurable
base address and address size for each Chip Select.
The base address is the lowest address in the address space for a chip select. This decides the
first location in data memory space where the connected memory hardware can be accessed.
Supports SRAM up to
Supports SDRAM up to
Four software configurable Chip Selects
Software configurable Wait State insertion
Clocked from the Fast Peripheral Clock at two times the CPU speed
– 512K Bytes using 2-port EBI
– 16M Bytes using 3-port EBI
– 128M bit using 3-port EBI
”Data Memory” on page 22
for details.
XMEGA A
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