ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 345

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.3
8077H–AVR–12/09
PDI Physical
(PDI_CLK), and the dedicated Test pin for data input and output (PDI_DATA). A JTAG interface
is also available on most devices, and this can be used for programming and debugging through
the 4-pin JTAG interface. The JTAG interface is IEEE std. 1149.1 compliant, and supports
boundary scan. Unless otherwise stated, all references to the PDI assumes access through the
PDI physical. Any external programmer or on-chip debugger/emulator can be directly connected
to these interfaces, and no external components are required.
Figure 29-1. The PDI with JTAG and PDI physical and closely related modules (grey)
The PDI physical layer handles the basic low-level serial communication. The physical layer
uses a bi-directional half-duplex synchronous serial receiver and transmitter (as a USART in
USRT mode). The physical layer includes start-of-frame detection, frame error detection, parity
generation, parity error detection, and collision detection.
The PDI is accessed through two pins:
In addition to these two pins, V
grammer/debugger and the device.
Figure 29-2. PDI connection
• PDI_CLK: PDI clock input (Reset pin).
• PDI_DATA: PDI data input/output (Test pin).
PDI_CLK
PDI_DATA
TDI
TMI
TCK
TDO
Program and Debug Interface (PDI)
Gnd
(physical layer)
(physical layer)
JTAG Physical
PDI Physical
Programmer/
Debugger
CC
and GND must also be connected between the External Pro-
Figure 29-2 on page 345
Controller
Vcc
PDI
PDI_CLK (RESET)
PDI_DATA (TEST)
shows a typical connection.
PDIBUS
Internal Interfaces
XMEGA A
Controller
Memories
OCD
NVM
NVM
345