SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 102

• Manufacturer Part Number: SAM9260
• Manufacturer: Atmel Corporation

Specifications of SAM9260

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 210 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Synchronous Receiver
Receiver Ready
Parity Error
Framing Error
Time-out
102
AT91X40 Series
When configured for synchronous operation (SYNC = 1), the receiver samples the RXD
signal on each rising edge of the Baud Rate clock. If a low level is detected, it is consid-
ered as a start. Data bits, parity bit and stop bit are sampled and the receiver waits for
the next start bit. See example in Figure 40.
Figure 40. Synchronous Mode: Character Reception
When a complete character is received, it is transferred to the US_RHR and the RXRDY
status bit in US_CSR is set. If US_RHR has not been read since the last transfer, the
OVRE status bit in US_CSR is set.
Each time a character is received, the receiver calculates the parity of the received data
bits, in accordance with the field PAR in US_MR. It then compares the result with the
received parity bit. If different, the parity error bit PARE in US_CSR is set.
If a character is received with a stop bit at low level and with at least one data bit at high
level, a framing error is generated. This sets FRAME in US_CSR.
This function allows an idle condition on the RXD line to be detected. The maximum
delay for which the USART should wait for a new character to arrive while the RXD line
is inactive (high level) is programmed in US_RTOR (Receiver Time-out). When this reg-
ister is set to 0, no time-out is detected. Otherwise, the receiver waits for a first character
and then initializes a counter which is decremented at each bit period and reloaded at
each byte reception. When the counter reaches 0, the TIMEOUT bit in US_CSR is set.
The user can restart the wait for a first character with the STTTO (Start Time-out) bit in
US_CR.
Calculation of time-out duration:
Example: 8-bit, parity enabled 1 stop
Sampling
SCK
RXD
True Start Detection
D0
Duration
D1
= Value x
D2
D3
4
D4
x
Bit period
D5
D6
D7
1354D–ATARM–08/02
Parity Bit
Stop Bit