SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 28

• Manufacturer Part Number: SAM9260
• Manufacturer: Atmel Corporation

Specifications of SAM9260

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 210 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Write Data Hold Time
28
AT91X40 Series
Figure 15. Early Read Protocol
Figure 16. Early Read Wait State
During write cycles in both protocols, output data becomes valid after the falling edge of
the NWE signal and remains valid after the rising edge of NWE, as illustrated in Figure
17. The external NWE waveform (on the NWE pin) is used to control the output data tim-
ing to guarantee this operation.
It is therefore necessary to avoid excessive loading of the NWE pins, which could delay
the write signal too long and cause a contention with a subsequent read cycle in stan-
dard protocol.
ADDR
MCKI
NWE
NRD
NCS
or
ADDR
MCKI
NWE
NCS
NRD
Write Cycle
Early Read Wait
Read Cycle
1354D–ATARM–08/02