SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 126

• Manufacturer Part Number: SAM9260
• Manufacturer: Atmel Corporation

Specifications of SAM9260

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 210 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Capture Operating Mode
Capture Registers A and B
(RA and RB)
Trigger Conditions
Status Register
126
AT91X40 Series
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode
Register). Capture Mode allows the TC Channel to perform measurements such as
pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which
are inputs.
Figure 46 shows the configuration of the TC Channel when programmed in Capture
Mode.
Registers A and B are used as capture registers. This means that they can be loaded
with the counter value when a programmable event occurs on the signal TIOA.
The parameter LDRA in TC_CMR defines the TIOA edge for the loading of register A,
and the parameter LDRB defines the TIOA edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded
since the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag
(LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten.
In addition to the SYNC signal, the software trigger and the RC compare trigger, an
external trigger can be defined.
Bit ABETRG in TC_CMR selects input signal TIOA or TIOB as an external trigger.
Parameter ETRGEDG defines the edge (rising, falling or both) detected to generate an
external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
The following bits in the status register are significant in Capture Operating Mode.
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•
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Note:
CPCS: RC Compare Status
There has been an RC Compare match at least once since the last read of the
status
COVFS: Counter Overflow Status
The counter has attempted to count past $FFFF since the last read of the status
LOVRS: Load Overrun Status
RA or RB has been loaded at least twice without any read of the corresponding reg-
ister, since the last read of the status
LDRAS: Load RA Status
RA has been loaded at least once without any read, since the last read of the status
LDRBS: Load RB Status
RB has been loaded at least once without any read, since the last read of the status
ETRGS: External Trigger Status
An external trigger on TIOA or TIOB has been detected since the last read of the
status
All the status bits are set when the corresponding event occurs and they are automati-
cally cleared when the Status Register is read.
1354D–ATARM–08/02