SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 29

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SAM9260

Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9260

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Wait States
Standard Wait States
1354D–ATARM–08/02
Figure 17. Data Hold Time
In early read protocol the data can remain valid longer than in standard read protocol
due to the additional wait cycle which follows a write access.
The EBI can automatically insert wait states. The different types of wait states are listed
below:
Each chip select can be programmed to insert one or more wait states during an access
on the corresponding device. This is done by setting the WSE field in the corresponding
EBI_CSR. The number of cycles to insert is programmed in the NWS field in the same
register.
Below is the correspondence between the number of standard wait states programmed
and the number of cycles during which the NWE pulse is held low:
For each additional wait state programmed, an additional cycle is added.
Standard wait states
Data float wait states
External wait states
Chip select change wait states
Early read wait states (see “Read Protocols” )
0 wait states1/2 cycle
1 wait state1 cycle
Data Output
ADDR
NWE
MCK
AT91X40 Series
29

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