TMPM380FYDFG Toshiba, TMPM380FYDFG Datasheet - Page 360

• Manufacturer Part Number: TMPM380FYDFG
• Manufacturer: Toshiba

Specifications of TMPM380FYDFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 16K
• Number Of Pins: 100
• Package: QFP(14×20)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 2
• I2c/sio (ch): 2
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 18
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

13.3.3 Serial Clock Generation Circuit
13.3.4 Receive Counter
13.3.5 Receive Control Unit
13.3.6 Receive Buffer
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I/O interface mode
Asynchronous (UART) mode :
I/O interface mode:
Asynchronous (UART) mode:
The receive counter is a 4-bit binary counter used in the asynchronous (UART) mode and is
up-counted by SIOCLK. Sixteen SIOCLK clock pulses are used in receiving a single data bit
while the data symbol is sampled at the seventh, eighth, and ninth pulses. From these three
samples, majority logic is applied to decide the received data.
The receive buffer is of a dual structure to prevent overrun errors. The receive shift register
stores the received data bit-by-bit. When a complete set of bits have been stored, they are
moved to the receive buffer (SC0BUF). At the same time, the receive buffer full flag
(SC0MOD2 “RBFLL”) is set to “1” to indicate that valid data is stored in the receive buffer.
However, if the receive FIFO is set enabled, the receive data is moved to the receive FIFO
and this flag is immediately cleared.
If the receive FIFO has been disabled (SCOFCNF <CNFG> = 0 and SC0MOD1<FDPX1:0>
=01), the INTRX0 interrupt is generated at the same time. If the receive FIFO has been
enabled (SCNFCNF <CNFG> = 1 and SC0MOD1<FDPX1:0> = 01), an interrupt will be
generated according to the SC0RFC <RIL1:0> setting.
This circuit generates basic transmit and receive clocks.
In the SCLK output mode with SC0CR <IOC> set to “0,” the RXD0 pin is sampled on the
rising edge of the shift clock output to the SCLK0 pin.
In the SCLK input mode with SC0CR <IOC> set to “1,” rising and falling edges are
detected according to the SC0CR <SCLKS> setting to generate the basic clock.
According to the settings of the serial control mode register SC0MOD0 <SC1:0>, either
the clock from the baud rate register, the system clock (f
the TMRB4 timer, or the external clock (SCLKO pin) is selected to generate the basic
clock, SIOCLK.
In the SCLK input mode with SC0CR <IOC> set to “1,” the serial receive data RXD0 pin
is sampled on the rising or falling edge of SCLK input depending on the SC0CR
<SCLKS> setting.
The receive control unit has a start bit detection circuit, which is used to initiate receive
operation when a normal start bit is detected.
In the SCLK output mode with the SC0CR <IOC> serial control register set to “0,” the
output of the previously mentioned baud rate generator is divided by 2 to generate the
basic clock.
TMPM380/M382 - 11 / 52 -
SYS
), the internal output signal of
TMPM380/M382