STPCD01 STMicroelectronics, STPCD01 Datasheet - Page 15

• Manufacturer Part Number: STPCD01
• Description: STPC CLIENT DATASHEET - PC COMPATIBLE EMBEDED MICROPROCESSOR
• Manufacturer: STMicroelectronics

2.2.SIGNAL DESCRIPTIONS
2.2.1.
PWGD System Reset/Power good. This input is
low when the reset switch is depressed. Other-
wise, it reflects the power supply’s power good
signal. PWGD is asynchronous to all clocks, and
acts as a negative active reset. The reset circuit
initiates a hard reset on the rising edge of PWGD.
XTALI 14.3MHz Pull Down (10 k )
XTALO 14.3MHz External Oscillator Input These
pins are the 14.318 MHz external oscillator input;
This clock is used as the reference clock for the in-
ternal frequency synthesizer to generate the
HCLK, CLK24M, GCLK2X and DCLK clocks.
Note: These pins are NOT 5V tolerant
HCLK Host Clock. This is the host 1X clock. Its
frequency can vary from 25 to 75 MHz. All host
transactions and PCI transactions are synchro-
nized to this clock. This clock drives the DRAM
controller to execute the host transactions. In nor-
mal mode, this output clock is generated by the in-
ternal PLL.
GCLK2X 80MHz Graphics Clock. This is the
Graphics 2X clock, which drives the graphics en-
gine and the DRAM controller to execute the
graphics and display cycles.
Normally GCLK2X is generated by the internal fre-
quency synthesizer, and this pin is an output. By
setting a bit in Strap Register 2, this pin can be
made an input so that an external clock can re-
place the internal frequency synthesizer.
DCLK 135MHz Dot Clock. This is the dot clock,
which drives graphics display cycles. Its frequency
can go from 8MHz (using internal PLL) up to 135
MHz, and it is required to have a worst case duty
cycle of 60-40.
DCLK_DIR Dot Clock Direction. Specifies if DCLK
is an input (0) or an output (1).
DEV_CLK 24MHz Peripheral Clock Output. This
24MHZ signal is provided as a convenience for
the system integration of a floppy disk driver func-
tion in an external chip.
2.2.2.
MA[11:0] Memory Address Output. These 12 mul-
tiplexed memory address pins support external
DRAM with up to 4K refresh. These include all
(see Table 4-2)
BASIC CLOCKS RESETS & XTAL
MEMORY INTERFACE
Issue 2.2 - October 13, 2000
16M x N and some 4M x N DRAM modules. The
address signals must be externally buffered to
support more than 16 DRAM chips. The timing of
these signals can be adjusted by software to
match the timings of most DRAM modules.
MD[63:0] Memory Data I/O. This is the 64-bit
memory data bus. If only half of a bank is populat-
ed, MD63-32 is pulled high, data is on MD31-0.
MD[40-0] are read by the device strap option reg-
isters during rising edge of PWGD.
RAS#[3:0] Row Address Strobe Output. There
are 4 active low row address strobe outputs, one
for each bank of the memory. Each bank contains
4 or 8-Bytes of data. The memory controller allows
half of a bank (4 Bytes) to be populated to enable
memory upgrade at finer granularity.
The RAS# signals drive the SIMMs directly with-
out any external buffering. These pins are always
outputs, but they can also simultaneously be in-
puts, to allow the memory controller to monitor the
value of the RAS# signals at the pins.
CAS#[7:0] Column Address Strobe Output. There
are 8 active low column address strobe outputs,
one for each Byte of the memory.
The CAS# signals drive the SIMMs either directly
or through external buffers.
These pins are always outputs, but they can also
simultaneously be inputs, to allow the memory
controller to monitor the value of the CAS# signals
at the pins.
MWE# Write Enable Output. Write enable speci-
fies whether the memory access is a read (MWE#
= H) or a write (MWE# = L). This single write ena-
ble controls all DRAMs. It can be externally buff-
ered to boost the maximum number of loads
(DRAM chips) supported.
The MWE# signals drive the SIMMs directly with-
out any external buffering.
2.2.3.
VCLK Pixel Clock Input.
VIN[7:0] YUV Video Data Input CCIR 601 or 656.
Time multiplexed 4:2:2 luminance and chromi-
nance data as defined in ITU-R Rec601-2 and
Rec656 (except for TTL input levels). This bus in-
terfaces with an MPEG video decoder output port
and typically carries a stream of Cb, Y, Cr, Y digit-
al video at VCLK frequency, clocked on the rising
edge (by default) of VCLK. A 54-Mbit/s ‘double’
Cb, Y, Cr, Y input multiplex is supported for double
encoding applications (rising and falling edge of
CKREF are operating).
VIDEO INPUT
PIN DESCRIPTION
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