STPCI01 STMicroelectronics, STPCI01 Datasheet - Page 19

• Manufacturer Part Number: STPCI01
• Description: STPC INDUSTRIAL - PC COMPATIBLE EMBEDED MICROPROC
• Manufacturer: STMicroelectronics

bus without any qualification of the command sig-
nal lines. MCS16# is always an input. The STPC
Industrial ignores this signal during IO and refresh
cycles.
IOCS16# IO Chip Select16. This signal is the de-
code of SA15-0 address pins of the ISA address
bus without any qualification of the command sig-
nals. The STPC Industrial does not drive IOCS16#
(similar to PC-AT design). An ISA master access
to an internal register of the STPC Industrial is ex-
ecuted as an extended 8-bit IO cycle.
REF# Refresh Cycle. This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Industrial performs a refresh cycle
on the ISA bus. It is used as an input when an ISA
master owns the bus and is used to trigger a re-
fresh cycle.
The STPC Industrial performs a pseudo hidden
refresh. It requests the host bus for two host
clocks to drive the refresh address and capture it
in external buffers. The host bus is then relin-
quished while the refresh cycle continues on the
ISA bus.
AEN Address Enable. Address Enable is enabled
when the DMA controller is the bus owner to indi-
cate that a DMA transfer will occur. The enabling
of the signal indicates to IO devices to ignore the
IOR#/IOW# signal during DMA transfers.
IOCHCK# IO Channel Check. IO Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. NMI signal be-
comes active upon seeing IOCHCK# active if the
corresponding bit in Port B is enabled.
GPIOCS# I/O General Purpose Chip Select 1.
This output signal is used by the external latch on
ISA bus to latch the data on the SD[7:0] bus. The
latch can be use by PMU unit to control the exter-
nal peripheral devices to power down or any other
desired function.
RTCRW# Real Time Clock RW#. This pin is used
as RTCRW#. This signal is asserted for any I/O
write to port 71h.
RTCDS# Real Time Clock DS . This pin is used as
RTCDS. This signal is asserted for any I/O read to
port 71h.
RTCAS# Real time clock address strobe. This sig-
nal is asserted for any I/O write to port 70h.
RMRTCCS# ROM/Real Time clock chip select.
This pin is a multi-function pin. This signal is as-
serted if a ROM access is decoded during a mem-
ory cycle. It should be combined with MEMR# or
MEMW# signals to properly access the ROM.
During an IO cycle, this signal is asserted if ac-
Issue 2.4 - February 11, 2002
cess to the Real Time Clock (RTC) is decoded. It
should be combined with IOR# or IOW# signals to
properly access the real time clock.
IRQ_MUX[3:0] Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They are
to be encoded before connection to the STPC In-
dustrial using ISACLK and ISACLKX2 as the input
selection strobes.
Note that IRQ8B, which by convention is connect-
ed to the RTC, is inverted before being sent to the
interrupt controller, so that it may be connected di-
rectly to the IRQ# pin of the RTC.
2.2.6 IPC (Combined with Serial Interface)
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Industrial before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
DREQ_MUX[1:0] ISA Bus Multiplexed DMA Re-
quest. These are the ISA bus DMA request sig-
nals. They are to be encoded before connection to
the STPC Industrial using ISACLK and ISACLKX2
as the input selection strobes.
TC ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
2.2.7 KEYBOARD/MOUSE INTERFACE
KBCLK, Keyboard Clock line. Keyboard data is
latched by the controller on each negative clock
edge produced on this pin. The keyboard can be
disabled by pulling this pin low by software control.
KBDATA, Keyboard Data Line. 11 bits of data are
shifted serially through this line when data is being
transferred. Data is synchronised to KBCLK.
MCLK, Mouse Clock line. Mouse data is latched
by the controller on each negative clock edge pro-
duced on this pin. The mouse can be disabled by
pulling this pin low by software control.
MDATA, Mouse Data Line. 11 bits of data are
shifted serially through this line when data is being
transferred. Data is synchronised to MCLK.
Note: MCLK and MDATA must be pulled when
the STPC Mouse interface is not used.
2.2.8 SERIAL INTERFACE
SIN1, SIN2 Input Serial input. Data is clocked in
using RCLK/16.
(Serial 1 combined with TFT Interface)
(Serial 2 combined with IPC)
PIN DESCRIPTION
19/69