STPCI01 STMicroelectronics, STPCI01 Datasheet - Page 17

• Manufacturer Part Number: STPCI01
• Description: STPC INDUSTRIAL - PC COMPATIBLE EMBEDED MICROPROC
• Manufacturer: STMicroelectronics

2.2. SIGNAL DESCRIPTIONS
2.2.2 BASIC CLOCKS AND RESETS
SYSRSTI# System Reset/Power good. This input
is low when the reset switch is depressed. Other-
wise, it reflects the power supply’s power good
signal. PWGD is asynchronous to all clocks, and
acts as a negative active reset. The reset circuit
initiates a hard reset on the rising edge of PWGD.
SYSRSTO# Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted buff-
ered version of this output and the PCI bus reset is
an externally buffered version of this output.
XTALI 14.3 MHz Crystal Input
XTALO 14.3 MHz Crystal Output. These pins are
the 14.318 MHz crystal input; This clock is used as
the reference clock for the internal frequency syn-
thesizer to generate the HCLK and CLK24M.
A 14.318 MHz Series Cut Quartz Crystal should
be connected between these two pins. Balance
capacitors of 15 pF should also be added. In the
event of an external oscillator providing the master
clock signal to the STPC Industrial device, the TTL
signal should be provided on XTALO.
PCI_CLKI 33 MHz PCI Input Clock
This signal must be connected to a clock genera-
tor and is usually connected to PCI_CLKO.
PCI_CLKO 33 MHz PCI Output Clock. This is the
master PCI bus clock output
ISA_CLK ISA Clock Output (also Multiplexer Se-
lect Line For IPC). This pin produces the Clock
signal for the ISA bus. It is also used with
ISA_CLK2X as the multiplexer control lines for the
Interrupt Controller Interrupt input lines. This is a
divided down version of the PCICLK or OSC14M.
ISA_CLKX2 ISA Clock Output (also Multiplexer
Select Line For IPC). This pin produces a signal at
twice the frequency of the ISA bus Clock signal. It
is also used with ISA_CLK as the multiplexer con-
trol lines for the Interrupt Controller Interrupt input
lines.
CLK14M ISA bus synchronisation clock. This is
the buffered 14.318 MHz clock to the ISA bus.
This clock also provides the reference clock to the
frequency synthesizer that generates GCLK2X
and DCLK.
Issue 2.4 - February 11, 2002
HCLK Host Clock. This is the host 1X clock. Its
frequency can vary from 50 MHz to 75 MHz. All
host transactions and PCI transactions are syn-
chronized to this clock. Host transactions execut-
ed by the DRAM controller are also driven by this
clock.
DEV_CLK 24 MHz Peripheral Clock (floppy
drive). This 24 MHZ signal is provided as a con-
venience for the system integration of a Floppy
Disk driver function in an external chip.
GCLK2X 80 MHz Graphics Clock. This is the
Graphics 2X clock, which drives the graphics en-
gine and the DRAM controller to execute the
graphics and display cycles.
Normally GCLK2X is generated by the internal fre-
quency synthesizer, and this pin is an output. By
setting a bit in Strap Register 2, this pin can be
made an input so that an external clock can re-
place the internal frequency synthesizer.
DCLK 135 MHz Dot Clock. This is the dot clock,
which drives graphics display cycles. Its frequency
can go from 8 MHz (using internal PLL) up to
135 MHz, and it is required to have a worst case
duty cycle of 60-40.
The direction can be controlled by a strap option
or an internal register bit.
2.2.3 MEMORY INTERFACE
MA[11:0] Memory Address. These 12 multiplexed
memory address pins support external DRAM with
up to 4K refresh. These include all 16M x N and
some 4M x N DRAM modules. The address sig-
nals must be externally buffered to support more
than 16 DRAM chips. The timing of these signals
can be adjusted by software to match the timings
of most DRAM modules.
MD[63:0] Memory Data. This is the 64-bit memory
data bus. If only half of a bank is populated,
MD63-32 is pulled high, data is on MD31-0.
MD20-0 are also used as inputs at the rising edge
of PWGD to latch in power-up configuration infor-
mation into the ADPC strap registers.
RAS#[3:0] Row Address Strobe. There are four
active low row address strobe outputs, one each
for each bank of the memory. Each bank contains
4 or 8 bytes of data. The memory controller allows
half of a bank (4 bytes) to be populated to enable
memory upgrade at finer granularity.
The RAS# signals drive the SIMMs directly with-
out any external buffering. These pins are always
outputs, but they can also simultaneously be in-
puts, to allow the memory controller to monitor the
value of the RAS# signals at the pins.
PIN DESCRIPTION
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