CS61305A-IL1 Cirrus Logic, Inc., CS61305A-IL1 Datasheet - Page 13

• Manufacturer Part Number: CS61305A-IL1
• Description: T1/E1 line interface
• Manufacturer: Cirrus Logic, Inc.

put from the phase selector feeds the clock and
data recovery circuits which generate the recov-
ered clock and sample the incoming signal at
appropriate intervals to recover the data. The jitter
tolerance of the receiver exceeds that shown in
Figure 12.
The CS61305A outputs a clock immediately upon
power-up and will lock onto the AMI data input
immediately. If loss of signal occurs, the RCLK
frequency will equal the ACLKI frequency.
DS157PP3
PEAK-TO-PEAK
Figure 12. Minimum Input Jitter Tolerance of Receiver
(unit intervals)
JITTER
300
138
100
28
10
.4
.1
1
1
1 : 2
AT&T 62411
10
RTIP
RRING
JITTER FREQUENCY
Minimum
Performance
100
300
700
1k
Figure 11. Receiver Block Diagram
(Hz)
10k
Detector
Slicer
Level
Edge
Data
100k
In the Hardware Mode, data at RPOS and RNEG
is stable and may be sampled on the rising edge
of the recovered clock. In the Extended Hardware
Mode, data at RDATA is stable and may be sam-
pled on the fallings edge of the recovered clock.
In the Host Mode, CLKE determines the clock
polarity for which output data is stable and valid
as shown in Table 5.
Jitter and Recovered Clock
The CS61305A is designed for error free clock
and data recovery from an AMI encoded data
X = Don’t care
(>(V+) - 0.2V)
(>(V+) - 0.2V)
MIDDLE
(<0.2V)
MODE
(pin 5)
(2.5V)
Continuously
HIGH
HIGH
LOW
Delay Line
Extraction
Calibrated
Sampling
Selector
Phase
Clock
Clock
Table 5. Data Output/Clock Relationship
Data
&
(pin 28)
CLKE
HIGH
LOW
X
X
RDATA
RPOS
RNEG
RCLK
RPOS
RNEG
RPOS
RNEG
RPOS
RNEG
DATA
ACLKI or
Oscillator in Jitter
Attenuator
SDO
SDO
CLOCK
RCLK
RCLK
RCLK
RCLK
SCLK
RCLK
RCLK
SCLK
RCLK
CS61305A
for Valid Data
Clock Edge
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Rising
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