CS61305A-IL1 Cirrus Logic, Inc., CS61305A-IL1 Datasheet - Page 16

• Manufacturer Part Number: CS61305A-IL1
• Description: T1/E1 line interface
• Manufacturer: Cirrus Logic, Inc.

Alarm Indication Signal
In the Extended Hardware Mode, the receiver sets
the output pin AIS high when unframed all-ones
condition (blue alarm) is detected using the crite-
ria of less than 3 zeros out of 2048 bit periods.
Line Code Encoder/Decoder
In the Extended Hardware Mode, three line codes
are available: AMI, B8ZS and HDB3. The input
to the encoder is TDATA. The outputs from the
decoder are RDATA and BPV (Bipolar Violation
Strobe). The encoder and decoder are selected
using the LEN2, LEN1, LEN0, TCODE and
RCODE pins as shown in Table 8.
Parallel Chip Select
In the Extended Hardware Mode, PCS can be
used to gate the digital control inputs: TCODE,
RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP
and TAOS. Inputs are accepted on these pins only
when PCS is low and will immediately change
the operating state of the device. Therefore, when
cycling PCS to update the operating state, the
digital control inputs should be stable for the en-
tire PCS low period. The digital control inputs are
ignored when PCS is high.
16
Selection)
Selection)
(Receiver
(Transmit
Decoder
Encoder
RCODE
TCODE
Table 8. Encoder/Decoder Selection
HIGH
HIGH
LOW
LOW
Encoder
Decoder
HDB3
HDB3
000
AMI Encoder
AMI Decoder
LEN 2/1/0
Encoder
Decoder
010-111
B8ZS
B8ZS
Power On Reset / Reset
Upon power-up, the IC is held in a static state
until the supply crosses a threshold of approxi-
mately 3 Volts. When this threshold is crossed,
the device will delay for about 10 ms to allow the
power supply to reach operating voltage. After
this delay, calibration of the delay lines used in
the transmit and receive sections commences. The
delay lines can be calibrated only if a reference
clock is present. The reference clock for the re-
ceiver is provided by ACLKI, or the crystal
oscillator. The reference clock for the transmitter
is provided by TCLK. The initial calibration
should take less than 20 ms.
In operation, the delay lines are continuously cali-
brated, making the performance of the device
independent of power supply or temperature vari-
ations. The continuous calibration function
eliminates any requirement to reset the line inter-
face when in operation. However, a reset function
is available which will clear all registers.
In the Hardware and Extended Hardware Modes,
a reset request is made by simultaneously setting
both the RLOOP and LLOOP pins high for at
least 200 ns. Reset will initiate on the falling edge
of the reset request (falling edge of RLOOP and
LLOOP). In the Host Mode, a reset is initiated by
simultaneously writing RLOOP and LLOOP to
the register. In either mode, a reset will set all reg-
isters to 0 and force the oscillator to its center
frequency before initiating calibration. A reset
will also set LOS high.
Serial Interface
In the Host Mode, pins 23 through 28 serve as a
microprocessor/microcontroller interface. One
on-board register can be written to via the SDI
pin or read from via the SDO pin at the clock rate
determined by SCLK. Through this register, a
CS61305A
DS157PP3