CS61305A-IL1 Cirrus Logic, Inc., CS61305A-IL1 Datasheet - Page 14

• Manufacturer Part Number: CS61305A-IL1
• Description: T1/E1 line interface
• Manufacturer: Cirrus Logic, Inc.

stream in the presence of more than 0.4 unit inter-
vals of jitter at high frequency. The clock
recovery circuit is also tolerant of long strings of
zeros. The edge of an incoming data bit causes
the circuitry to choose a phase from the delay line
which most closely corresponds with the arrival
time of the data edge, and that clock phase trig-
gers a pulse which is typically 140 ns in duration.
This phase of the delay line will continue to be
selected until a data bit arrives which is closer to
another of the 13 phases, causing a new phase to
be selected. The largest jump allowed along the
delay line is six phases.
When an input signal is jitter free, the phase se-
lection will occasionally jump between two
adjacent phases resulting in RCLK jitter with an
amplitude of 1/13 UIpp. These single phase
jumps are due to differences in frequency of the
incoming data and the calibration clock input to
ACLKI. For T1 operation the instantaneous pe-
riod can be 14/13 * 648 ns = 698 ns or 12/13 *
648 ns = 598 ns when adjacent clock phases are
chosen. As long as the same phase is chosen, the
period will be 648 ns. Similar calculations hold
for the E1 rate.
The clock recovery circuit is designed to accept at
least 0.4 UI of jitter at the receiver. Since the data
stream contains information only when ones are
transmitted, a clock/data recovery circuit must as-
sume a zero when no signal is measured during a
bit period. Likewise, when zeros are received, no
information is present to update the clock recov-
ery circuit regarding the trend of a signal which is
jittered. The result is that two ones that are sepa-
rated by a string of zeros can exhibit maximum
deviation in pulse arrival time. For example, one
half of a period of jitter at 100 kHz occurs in 5
tude is 0.4 UI, then a one preceded by seven zeros
can have maximum displacement in arrival time,
i.e. either 0.4 UI too early or 0.4 UI too late. The
data recovery circuit correctly assigns a received
bit to its proper clock period if it is displaced by
14
s, which is 7.7 T1 bit periods. If the jitter ampli-
less than 6/13 of a bit period from its optimal lo-
cation. Theoretically, this would give a jitter
tolerance of 0.46 UI. The actual jitter tolerance of
the CS61305A is only slightly less than the ideal.
In the event of a maximum jitter hit, the RCLK
clock period immediately adjusts to align itself
with the incoming data and prepare to accurately
place the next one, whether it arrives one period
later, or after another string of zeros and is dis-
placed by jitter. For a maximum early jitter hit,
RCLK will have a period of 7/13 * 648 ns = 349
ns. For a maximum late jitter hit, RCLK will have
a period of 19/13 * 648 ns = 947 ns.
Loss of Signal
Receiver loss of signal is indicated upon receiv-
ing 175 consecutive zeros. A digital counter
counts received zeros based on RCLK cycles. A
zero input is determined either when zeros are re-
ceived, or when the received signal amplitude
drops below a 0.3 V peak threshold.
The receiver reports loss of signal by setting the
Loss of Signal pin, LOS, high. If the serial inter-
face is used, the LOS bit will be set and an
interrupt issued on INT. LOS will go low (and
flag the INT pin again if serial I/O is used) when
a valid signal is detected. Note that in the Host
Mode, LOS is simultaneously available from both
the register and pin 12.
In a loss of signal state, the RCLK frequency will
be equal to the ACLKI frequency since ACLKI is
being used to calibrate the clock recovery circuit.
Received data is output on RPOS/RNEG regard-
less of LOS status. LOS returns to logic zero
when 3 ones are received out of 32 bit periods
containing no more than 15 consecutive zeros.
Also, a power-up or manual reset will set LOS
high.
CS61305A
DS157PP3