CS61305A-IL1 Cirrus Logic, Inc., CS61305A-IL1 Datasheet - Page 21

• Manufacturer Part Number: CS61305A-IL1
• Description: T1/E1 line interface
• Manufacturer: Cirrus Logic, Inc.

LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)
LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)
MODE - Mode Select, Pin 5.
PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode)
RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode)
RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes)
SCLK - Serial Clock, Pin 27. (Host Mode)
SDI - Serial Data Input, Pin 24. (Host Mode)
DS157PP3
Determines the shape and amplitude of the transmitted pulse to accommodate several cable types
and lengths. See Table 3 for information on line length selection. These pins also control the
receiver slicing level.
Setting LLOOP to a logic 1 routes the transmit clock and data through to the receive clock and
data pins. TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request.
Inputs on RTIP and RRING are ignored during LLOOP. The jitter attenuator is bypassed.
Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.
Driving the MODE pin high places the line interface in the Host Mode. In the Host mode, a serial
control port is used to control the line interface and determine its status. Grounding the MODE
pin places the line interface in the Hardware Mode, where configuration and status are controlled
by discrete pins. Floating the MODE pin or driving it to +2.5 V places the device in Extended
Hardware Mode, where configuration and status are controlled by discrete pins. When floating
MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see
Table 2).
Setting PCS low causes the line interface to accept the TCODE, RCODE, LEN0, LEN1, LEN2,
RLOOP, LLOOP and TAOS inputs.
Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting
RCODE high enables the AMI receiver decoder (see Table 8).
Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter
attenuator and through the driver back to the line. The recovered signal is also sent to RCLK and
RPOS/RNEG (or RDATA). Any TAOS request is ignored.
Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.
Clock used to read or write the serial port registers. SCLK can be either high or low when the line
interface is selected using the CS pin.
Input for the input data register. Sampled on the rising edge of SCLK.
CS61305A
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