MT28F322D20 Micron Technology, MT28F322D20 Datasheet - Page 15

• Manufacturer Part Number: MT28F322D20
• Description: (MT28F322D18 / MT28F322D20) FLASH MEMORY
• Manufacturer: Micron Technology

PROGRAMMING OPERATIONS
PROGRAM SETUP and ALTERNATE PROGRAM SETUP
(see Table 3).
40h command code on DQ0–DQ7), the WSM takes over
and correctly sequences the device to complete the PRO-
GRAM operation. Monitoring of the WRITE operation is
possible through the status register (see the Status Regis-
ter section). During this time, the CSM responds only to
a PROGRAM SUSPEND command until the PROGRAM
operation has been completed, after which all commands
to the CSM become valid again. The PROGRAM opera-
tion can be suspended by issuing a PROGRAM SUSPEND
command (B0h). Once the WSM has reached the sus-
pend state, it allows the CSM to respond only to READ
ARRAY, READ STATUS REGISTER, READ PROTECTION
CONFIGURATION, READ QUERY, PROGRAM SETUP, or
PROGRAM RESUME. During the PROGRAM SUSPEND
operation, array data should be read from an address
other than the one being programmed. To resume the
PROGRAM operation, a PROGRAM RESUME command
(D0h) must be issued to cause the CSM to clear the
suspend state previously set (see Figure 4 for program-
ming operation and Figure 5 for program suspend and
program resume).
PROGRAM operation. During programming, V
remain in the appropriate V
the recommended operating conditions table.
ERASE OPERATIONS
in an array block to “1s.” After BLOCK ERASE CONFIRM
is issued, the CSM responds only to an ERASE SUSPEND
command until the WSM completes its task.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
There are two CSM commands for programming:
After the desired command code is entered (10h or
Taking RST# to V
An ERASE operation must be used to initialize all bits
IL
during programming aborts the
PP
voltage range as shown in
PP
must
ASYNC/PAGE/BURST FLASH MEMORY
15
within the address block to logic 1s. Erase is accom-
plished only by blocks; data at single address locations
within the array cannot be erased individually. The block
to be erased is selected by using any valid address within
that block. Block erasure is initiated by a command se-
quence to the CSM: BLOCK ERASE SETUP (20h) followed
by BLOCK ERASE CONFIRM (D0h) (see Figure 6). A two-
command erase sequence protects against accidental
erasure of memory contents.
plete, the WSM automatically executes a sequence of
events to complete the block erasure. During this se-
quence, the block is programmed with logic 0s, data is
verified, all bits in the block are erased to logic 1 state, and
finally verification is performed to ensure that all bits are
correctly erased. The ERASE operation may be moni-
tored through the status register (see the Status Register
section).
ERASE SUSPEND command (B0h) can be entered to di-
rect the WSM to suspend the ERASE operation. Once the
WSM has reached the suspend state, it allows the CSM to
respond only to the READ ARRAY, READ STATUS REGIS-
TER, READ QUERY, READ CHIP PROTECTION CON-
FIGURATION, PROGRAM SETUP, PROGRAM RESUME,
ERASE RESUME and LOCK SETUP (see the Block Locking
section). During the ERASE SUSPEND operation, array
data must be read from a block other than the one being
erased. To resume the ERASE operation, an ERASE RE-
SUME command (D0h) must be issued to cause the CSM
to clear the suspend state previously set (see Figure 7). It
is also possible to suspend an ERASE in any bank and
initiate a WRITE to another block in the same bank. After
the completion of a WRITE, an ERASE can be resumed by
writing an ERASE RESUME command.
Block erasure inside the memory array sets all bits
When the BLOCK ERASE CONFIRM command is com-
During the execution of an ERASE operation, the
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2 MEG x 16
©2002, Micron Technology, Inc.