MT28F322D20 Micron Technology, MT28F322D20 Datasheet - Page 28

• Manufacturer Part Number: MT28F322D20
• Description: (MT28F322D18 / MT28F322D20) FLASH MEMORY
• Manufacturer: Micron Technology

ASYNCHRONOUS PAGE READ MODE
mode over the whole memory array. The page size can be
customized at the factory to four or eight words as re-
quired; but if no specification is made, the normal size is
eight words. The initial portion of the page mode cycle is
the same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0–A2 allows random ac-
cess of other words in the page.
V
VOLTAGES
and erase with V
V
ity with existing programming equipment.
erations when V
and 10 cumulative hours when V
programming voltage can be held LOW for absolute hard-
ware write protection of all blocks in the Flash device.
When V
tion will result in an error, prompting the corresponding
status register bit (SR3) to be set.
tors the V
allowed only when V
Table 13.
WRITE/ERASE operation will be prevented.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
PP
In Factory (V
PP
In System (V
After power-up or reset, the device operates in page
The Flash devices provide in-system programming
The device can withstand 100,000 WRITE/ERASE op-
In addition to the flexible block locking, the V
During WRITE and ERASE operations, the WSM moni-
When V
(V
/V
PP
CC
PP
2
) mode programming is offered for compatibil-
PP
is below V
PROGRAM AND ERASE
CC
voltage level. WRITE/ERASE operations are
is below V
PP
PP
PP
1
2
PP
)
)
= V
V
in the 0.9V–2.2V range (V
PPLK
PP
PP
PP
Table 13
1
, any PROGRAM or ERASE opera-
is within the ranges specified in
Range (V)
or 100 WRITE/ERASE operations
LKO
MIN
11.4
0.9
or V
PP
PP
= V
is below V
PP
2
.
PP
MAX
2.25
12.6
1
). The 12V
PPLK
, any
PP
ASYNC/PAGE/BURST FLASH MEMORY
28
STANDBY MODE
level on CE# and RST# to enter the standby mode. In the
standby mode, the outputs are High-Z. Applying a CMOS
logic HIGH level on CE# and RST# reduces the current to
I
operation or during programming, the device continues
to draw current until the operation is complete.
AUTOMATIC POWER SAVE MODE (APS)
when the array is not being read and the device is in the
active mode. During this time the device switches to the
automatic power save mode. When the device switches
to this mode, I
Further power savings can be realized by applying a logic
HIGH level to CE# to place the device in standby mode.
The low level of power is maintained until another opera-
tion is initiated. In this mode, the I/Os retain the data
from the last memory address read until a new address is
read. This mode is entered automatically if no address or
control signals toggle.
DEVICE RESET
must be asserted (RST# = V
reset, the devices can be accessed for a READ operation
with a delayed access time of
of RST#. The circuitry used for generating the RST# signal
needs to be common with the rest of the system reset to
ensure that correct system initialization occurs. Please
refer to the timing diagram for further details.
POWER-UP SEQUENCE
to properly initialize internal chip operations:
should be brought to V
the rise time of RST (10%–90%) should be < 10µs.
CC
4
I
Substantial power savings are realized during periods
To correctly reset the Flash devices, the RST# signal
The following power-up sequence is recommended
• At power-up, RST# should be kept at V
• V
• V
When the power-up sequence is completed, RST#
CC
(MAX). If the device is deselected during an ERASE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
V
supply current is reduced by applying a logic HIGH
CC
CC
PP
Q should not come up before V
should be kept at V
reaches V
CC
is reduced to a level comparable to I
CC
(MIN).
IH
. To ensure a proper power-up,
IL
IL
) for a minimum of
t
to maximize data integrity.
RWH from the rising edge
2 MEG x 16
©2002, Micron Technology, Inc.
CC
IL
.
for 2µs after
t
RP. After
CC
4
.