MT28F322D20 Micron Technology, MT28F322D20 Datasheet - Page 23

• Manufacturer Part Number: MT28F322D20
• Description: (MT28F322D18 / MT28F322D20) FLASH MEMORY
• Manufacturer: Micron Technology

HOLD DATA OUTPUT CONFIGURATION
many clocks data will be held valid. (See Figure 10.)
WAIT# CONFIGURATION
the WAIT# output signal. The WAIT# signal can be active
during an output delay or one data cycle before delay
when continuous burst length is enabled. WAIT# = 1
indicates valid data when RCR8 = 0. WAIT# = 0 indicates
invalid data when RCR8 = 0. The setting of wait before or
wait during RCR8 will depend on the system and CPU
characteristic. If RCR3 = 1 (no wrap mode), then WAIT#
can also be enabled in a four- or eight-word burst if the
no-wrap burst crosses the first eight-word boundary.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
STARTING
ADDRESS
The hold data output configuration specifies for how
The wait configuration bit, RCR8, sets the behavior of
(DEC)
14
15
14
15
...
...
...
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
.
WRAP
RCR3
...
...
...
0
0
0
0
0
0
0
0
0
0
WRAP
RCR3
NO
...
...
...
1
1
1
1
1
1
1
1
1
1
LINEAR
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
…
...
...
...
...
BURST LENGTH
Sequence and Burst Length
4-WORD
INTERLEAVED
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
NA
NA
NA
NA
Table 10
...
...
...
ASYNC/PAGE/BURST FLASH MEMORY
23
signal to drive banks of the devices. An internal 1MΩ
pull-up resistor holds WAIT# = 1 and allows wired OR’ing
multiple bank configurations, as shown in Figure 11.
BURST SEQUENCE
data in synchronous burst mode. It can be programmed
as either linear or interleaved burst order. Continuous
burst length only supports linear burst order. See Table
10 for more details.
7-8-9-10-11-12-13-14
6-7-8-9-10-11-12-13
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
3-4-5-6-7-8-9-10
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
A Flash controller (CPU) is able to use this output
The burst sequence specifies the address order of the
LINEAR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
...
...
...
BURST LENGTH
8-WORD
INTERLEAVED
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NA
NA
NA
NA
NA
NA
NA
NA
...
...
...
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
14-15-16-17-18-19-20-..
15-16-17-18-19-20-21-..
6-7-8-9-10-11-12-13-…
2 MEG x 16
7-8-9-10-11-12-13…
6-7-8-9-10-11-12-…
6-7-8-9-10-11-12…
5-6-7-8-9-10-11-…
5-6-7-8-9-10-11…
4-5-6-7-8-9-10-…
4-5-6-7-8-9-10-…
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
CONTINUOUS
©2002, Micron Technology, Inc.
LINEAR
BURST
...
...
...