AN2184 Freescale Semiconductor / Motorola, AN2184 Datasheet - Page 22

• Manufacturer Part Number: AN2184
• Description: MCF5272 Interrupt Service Routine for the Physical Layer Interface Controller
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Assembly Code Interrupt Vector Generation
All external interrupt inputs are edge-sensitive where the active edge is programmable. The active edge is
programmable. An interrupt request must be held valid for at least three consecutive CPU clock cycles to
be considered a valid input. Each interrupt input can have its priority programmed by programming the
xIPL(2-0) bits in the interrupt control registers. When the ColdFire core responds to a request with an
interrupt acknowledge cycle, as is standard in MC52xx implementations, the interrupt controller logic will
forward the correct vector depending on the original source of the interrupt. Software can clear pending
interrupts from any source via the registers in the interrupt controller logic, and can program the location of
the block of vectors used for interrupt sources via the programmable interrupt vector register. For an
interrupt to be successfully processed, RAM must be available for the stack, and often this RAM will be
selected by one of the programmable chip selects. So upon system startup there is a brief period where
RAM is not available for the stack. To ensure no problems resulting from interrupts (particularly of priority
level 7) during this period, there is an interlock which prevents any interrupt from reaching the ColdFire
core until the first write cycle to the programmable interrupt vector register (PIVR). The user should ensure
that both RAM chip selects and the system stack are set up prior to this write operation.
The interrupt controller includes daisy-chaining functions in order to avoid contention when the ColdFire
core issues an interrupt acknowledge cycle. So if more than one interrupt source has the same interrupt
priority level (IPL), they are daisy chained with INT1 being the highest priority. There are four interrupt
control registers which control the interrupt priorities for the external general purpose latched interrupt
input signals and the internal I/O modules’ signals. These registers allow software to reset any pending
interrupts from these external interrupt lines or internal modules. There are up to 32 interrupt inputs, each
of which has four bits assigned to it in these registers. The registers can be read or written at any time.
When read, the data returned is the last value that was written to the register, with the exception of the reset
bits, which are transitory functions. The registers can be accessed by either long word (32-bit), word
(16-bit), or byte (8-bit) data transfer instructions. An 8-bit write to one-half of a register will leave the other
half intact.
7.2 Interrupt Vector Generation
Pending interrupts are presented to the MCF52xx core in order of priority. The core responds to an
interrupt request by initiating an interrupt acknowledge cycle to receive a vector number, which allows the
core to locate the interrupt’s service routine. The interrupt controller is able to identify the source of the
interrupt, which is being acknowledged and indicates this to the interrupt module mapper. The mapper
determines which slave bus module is to provide the interrupt vector for the identified interrupt source. In
most instances it is the interrupt controller itself which will provide the interrupt vector in which case the
following procedure is used. The three most significant bits of the interrupt vector are programmed by the
user in the programmable interrupt vector register.
7.3 Prioritization Level: ICR2 Register
The interrupt control registers (ICRx) allow the user to define which interrupt priority level (IPL), each of
these peripheral sources will use. For those modules whose interrupt sources are mapped to the interrupt
controller for the vector source, the programmable interrupt vector register (PIVR) allows the user to
define a particular vector number to be presented when the respective module receives an interrupt
acknowledge from the MCF52xx core via the interrupt controller logic. The interrupt vector register is
initialized upon system reset with the uninitialized interrupt vector (hexadecimal 0x0F), and must be
programmed with the required vector number for normal operation. It is important not to use reserved
interrupt vector locations for this purpose. The dedicated ICRx for the periodic and aperiodic interrupts is
ICR2.
22
MCF5272 Interrupt Service Routine
For More Information On This Product,
Go to: www.freescale.com