AN2184 Freescale Semiconductor / Motorola, AN2184 Datasheet - Page 8

• Manufacturer Part Number: AN2184
• Description: MCF5272 Interrupt Service Routine for the Physical Layer Interface Controller
• Manufacturer: Freescale Semiconductor / Motorola

4.2.2 Monitor Channel Transmit
The P n GMT registers are 16-bit registers containing the control and monitor channel bits to be transmitted
for each of the four ports on the MCF5272. A byte of monitor channel data to be transmitted on a certain
port is put into an associated register using the format shown in Figure 6 and described in Table 2. A
maskable interrupt is generated when this byte of data has been successfully transmitted.
15–10
GCI/IDL and the MCF5272 Monitor Channel Registers
8
Reset
Bits
Field
Addr
R/W
9
15–11
Name
Bits
7–0
15
10
—
9
8
L
Reserved, should be cleared.
Last.
0 Default reset value
1 Set by the CPU. Indicates to the monitor channel controller to transmit the end of message signal
The L bit is automatically cleared by the GCI controller.
Name
on the E bit. Both P n GMT[L] and P n GMT[R] must be set for the monitor channel controller to send
the end of message signal.
EOM
MC
AB
—
M
MBAR + 0x368 (P0GMT); 0x36A (P1GMT); 0x36C (P2GMT); 0x36E (P3GMT)
Figure 6. GCI Monitor Channel Transmit Register (P n GMT)
—
Reserved, should be cleared.
End of message.
0 Default at reset.
1 Indicates to the CPU that an end-of-message condition has been recognized on
Abort.
0 Default at reset.
1 Indicates that the GCI controller has recognized an abort condition and is
Monitor change.
0 Default at reset.
1 Indicates to the CPU that the monitor channel data byte written to the respective
Monitor channel data byte. These bits are written by the monitor channel controller
when valid monitor channel bytes are received.
the E bit. EOM is automatically cleared when the P n GMR register has been read
by the CPU.
acknowledging the abort. It is automatically cleared by the CPU when the
P n GMR register has been read.
P n GMR register has changed and that the data is available for processing. This
bit is automatically cleared by the CPU when the P n GMR register has been
read. Clearing this bit also clears the aperiodic GMR interrupt.
Freescale Semiconductor, Inc.
Table 1.
Table 2. P n GMT Register Field Descriptions
For More Information On This Product,
MCF5272 Interrupt Service Routine
P n GMR
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10
0000_0000_0000_0000
9
L
Register Field Descriptions
Read/Write
R
8
Description
Description
7
M
0