AN2184 Freescale Semiconductor / Motorola, AN2184 Datasheet - Page 7

• Manufacturer Part Number: AN2184
• Description: MCF5272 Interrupt Service Routine for the Physical Layer Interface Controller
• Manufacturer: Freescale Semiconductor / Motorola

3.3 Command Indicate Operation
The command/indicate, or C/I channel, is used to activate and deactivate any GCI devices. Some control
functions (such as loopbacks) are also supported over the C/I channel. C/I codes are four bits in length and
must be received for two consecutive GCI frames before they are acted on. C/I channel bits are numbered
bit 3 through 0, with bit 3 being the most significant. The C/I/ channel bits are transmitted starting with bit
3.
Part IV GCI/IDL and the MCF5272
This section gives a brief description of the internal registers in the PLIC.
4.1 Data Registers
For both GCI and IDL modes of operation, the maximum data rate transmitted for each digital port is
144 kbps (two 64-kbps B channels and one 16-kbps D channel). Frames of B1, B2, and D channels are
packed together in P n RB x /P n TB x registers (with x = 1, 2, 3, 4) for receive and transmit direction
respectively. Since the reception and transmission of information on the GCI/IDL interface is
deterministic, a common interrupt is generated at 2 kHz. It is expected that a common interrupt service
routine will be programmed to service the transmit and receive registers. After reset, the B and D channel
shift registers and shadow registers are initialized to all 1’s. For more information about the data registers,
please refer to the MCF5272 User’s Manual .
4.2 Monitor Channel Registers
This section describes receive and transmit channels.
4.2.1 Monitor Channel Receive
The P n GMR registers are 16-bit registers containing the received monitor channel bits for each of the four
receive ports on the MCF5272. A byte of monitor channel data received on a certain port is put into an
associated register using the format shown in Figure 5 and described in Table 1. A maskable interrupt is
generated when a byte is written into any of the four available MCF5272 ports.
Reset
Field
Addr
R/W
15
—
MBAR + 0x360 (P0GMR); 0x362 (P1GMR); 0x364 (P2GMR); 0x366 (P3GMR)
Figure 5. GCI Monitor Channel Receive Register (
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MCF5272 Interrupt Service Routine
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10
AB
0000_0000_1111_1111
GCI/IDL and the MCF5272 Command Indicate Operation
9
Read Only
MC
8
7
P n GMR
M
)
0
7