IDT72V3644L10PF IDT, Integrated Device Technology Inc, IDT72V3644L10PF Datasheet - Page 13

• Manufacturer Part Number: IDT72V3644L10PF
• Description: IC FIFO 2048X36 10NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3644L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3644L10PF

When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory
for reading to the output register. When the Empty Flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
that reads data from its array. For both the FWFT and IDT Standard modes,
the FIFO read pointer is incremented each time a new word is clocked to its
output register. The state machine that controls an Output Ready flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2.
to the FIFO output register in a minimum of three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port Clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
output register.
TABLE 5 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
In the IDT Standard mode, the Empty Flag (EFA, EFB) function is selected.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
operation necessary), it is not included in the FIFO memory count.
operation necessary), it is not included in the FIFO memory count.
(X1+1) to [256-(Y1+1)]
(X2+1) to [256-(Y2+1)]
IDT72V3624
(256-Y1) to 255
IDT72V3624
(256-Y2) to 255
1 to X1
1 to X2
256
256
0
0
(3)
(3)
Number of Words in FIFO Memory
Number of Words in FIFO Memory
(X2+1) to [512-(Y2+1)]
(X1+1) to [512-(Y1+1)]
IDT72V3634
(512-Y2) to 511
IDT72V3634
(512-Y1) to 511
1 to X2
1 to X1
512
512
0
0
(3)
(3)
(1,2)
(1,2)
TM
(X1+1) to [1,024-(Y1+1)]
(X2+1) to [1,024-(Y2+1)]
WITH BUS-MATCHING
(1,024-Y1) to 1,023
(1,024-Y2) to 1,023
IDT72V3644
IDT72V3644
1 to X1
1 to X2
1,024
13
1,024
0
0
Flag will indicate the presence of data available for reading in a minimum of
two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag
is LOW if a word in memory is the next data to be sent to the FlFO output register
and two cycles of the port Clock that reads data from the FIFO have not elapsed
since the time the word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing clock occurs,
forcing the Empty Flag HIGH; only then can data be read.
clock begins the first synchronization cycle of a write if the clock transition occurs
at time t
can be the first synchronization cycle (see Figures 15, 16, 17, and 18).
FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)
function is selected. In IDT Standard mode, the Full Flag (FFA and FFB)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB)
(3)
(3)
SKEW1
or greater after the write. Otherwise, the subsequent clock cycle
EFB/ORB
EFA/ORA
H
H
H
H
Synchronized
L
Synchronized
H
H
H
H
L
to CLKB
to CLKA
COMMERCIAL TEMPERATURE RANGE
AEB
AEA
H
H
H
H
H
H
L
L
L
L
AFA
Synchronized
AFB
Synchronized
H
H
H
H
H
H
L
L
L
L
to CLKA
to CLKB
FFA/IRA
FFB/IRB
H
H
H
H
L
H
H
H
H
L