IDT72V3644L10PF IDT, Integrated Device Technology Inc, IDT72V3644L10PF Datasheet - Page 25

• Manufacturer Part Number: IDT72V3644L10PF
• Description: IC FIFO 2048X36 10NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3644L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3644L10PF

NOTES:
1. t
2. If Port B size is word or byte, t
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
B0-B35
A0-A35
W/RA
W/RB
If the time between the CLKB edge and the rising CLKA edge is less than t
cycle later than shown.
CLKB
CLKA
SKEW1
MBA
CSB
MBB
ORA
CSA
ENB
ENA
IRB
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
FIFO2 Empty
LOW
LOW
HIGH
LOW
LOW
LOW
Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
t
t
ENS2
ENS2
t
DS
SKEW1
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
W1
Old Data in FIFO2 Output Register
t
SKEW1
t
t
t
DH
ENH
ENH
(1)
t
CLKH
1
t
CLK
SKEW1
t
TM
CLKL
WITH BUS-MATCHING
, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
t
CLKH
25
2
t
CLK
t
REF
3
t
A
t
CLKL
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
REF
t
ENH
W1
4664 drw19