IDT72V3644L10PF IDT, Integrated Device Technology Inc, IDT72V3644L10PF Datasheet - Page 31

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IDT72V3644L10PF

Manufacturer Part Number
IDT72V3644L10PF
Description
IC FIFO 2048X36 10NS 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V3644L10PF

Function
Asynchronous, Synchronous
Memory Size
72K (2K x 36)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V3644L10PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V3644L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V3644L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will be
NOTES:
1. t
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3624, 512 for the IDT72V3634, 1,024 for the IDT72V3644.
4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKB
CLKA
A0-A35
B0-B35
ENB
AFB
ENA
indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data
(B9-B35 will be indeterminate).
CLKB
MBF1
CLKA edge is less than t
CLKA
W/RA
SKEW2
W/RB
CSB
CSA
MBA
ENA
MBB
ENB
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
[D-(Y2+1)] Words in FIFO2
SKEW2
t
ENS2
, then AFB may transition HIGH one CLKB cycle later than shown.
Figure 26. Timing for AFB
Figure 27. Timing for Mail1 Register and MBF1
t
t
t
t
ENS2
ENS2
ENS1
ENS2
t
FIFO1 Output Register
EN
t
t
PAF
ENH
t
DS
W1
AFB
AFB
AFB
AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
t
MDV
t
t
t
t
DH
t
ENH
ENH
ENH
ENH
t
t
PMF
ENS2
t
TM
PMR
WITH BUS-MATCHING
MBF1
MBF1
MBF1
MBF1 Flag (IDT Standard and FWFT Modes)
31
(D-Y2) Words in FIFO2
t
SKEW2
t
ENH
W1 (Remains valid in Mail1 Register after read)
(1)
1
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
ENH
t
PMF
2
t
PAF
t
DIS
4664 drw29
4664 drw28

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