IDT72V3644L10PF IDT, Integrated Device Technology Inc, IDT72V3644L10PF Datasheet - Page 18

• Manufacturer Part Number: IDT72V3644L10PF
• Description: IC FIFO 2048X36 10NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3644L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3644L10PF

NOTES:
1. t
2. CSA=LOW, W/RA=HIGH,MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
NOTES:
1. t
2. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA and FFB/IRB is set HIGH.
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).
FS1/SEN
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
FS1,FS0
FFA/IRA
FFB/IRB
FFA/IRA
FFB/IRB
FS0/SD (3)
A0-A35
edge of CLKB is less than t
edge of CLKB is less than t
SKEW1
SKEW1
MRS1,
MRS2
CLKA
CLKB
CLKA
MRS1,
MRS2
CLKB
ENA
SPM
SPM
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes)
is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
t
t
FSS
FSS
4
0,0
t
t
FSS
FSS
4
SKEW1
SKEW1
4
t
t
FSH
FSH
, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
1
t
FSH
t
SPH
2
AFA Offset (Y1) MSB
t
SENS
AFA Offset
t
t
SDS
WFF
t
DS
(Y1)
TM
WITH BUS-MATCHING
t
ENS2
t
DH
t
t
SENH
SDH
18
AEB Offset
(X1)
t
ENH
AFB Offset
(Y 2)
AEA Offset (X2) LSB
t
SENS
t
SDS
COMMERCIAL TEMPERATURE RANGE
AEA Offset
(X 2)
t
SKEW (1)
t
t
SENH
SDH
1
t
SKEW1
First Word to FIFO1
(1)
2
t
t
WFF
WFF
4664 drw07
t
4664 drw08
WFF