IDT72V3644L10PF IDT, Integrated Device Technology Inc, IDT72V3644L10PF Datasheet - Page 14

• Manufacturer Part Number: IDT72V3644L10PF
• Description: IC FIFO 2048X36 10NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3644L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3644L10PF

writes data to its array. For both FWFT and IDT Standard modes, each time
a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock have elapsed since
the next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
begins the first synchronization cycle of a read if the clock transition occurs at
time t
can be the first synchronization cycle (see Figures 19, 20, 21, and 22).
ALMOST-EMPTY FLAGS (AEA, AEB)
data from its array. The state machine that controls an Almost-Empty flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2.
The almost-empty state is defined by the contents of register X1 for AEB and
register X2 for AEA. These registers are loaded with preset values during a
FIFO reset, programmed from Port A, or programmed serially (see Almost-
Empty flag and Almost-Full flag offset programming section). An Almost-
Empty flag is LOW when its FIFO contains X or less words and is HIGH when
its FIFO contains (X+1) or more words. A data word present in the FIFO output
register has been read from memory.
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not elapsed since
the write that filled the memory to the (X+1) level. An Almost-Empty flag is set
HIGH by the second LOW-to-HIGH transition of its synchronizing clock after
the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition
of an Almost-Empty flag synchronizing clock begins the first synchronization
cycle if it occurs at time t
words. Otherwise, the subsequent synchronizing clock cycle may be the first
synchronization cycle. (See Figure 23 and 24).
ALMOST-FULL FLAGS (AFA, AFB)
data to its array. The state machine that controls an Almost-Full flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-full, almost-full-1, or almost-full-2. The almost-full state
is defined by the contents of register Y1 for AFA and register Y2 for AFB. These
registers are loaded with preset values during a FlFO reset, programmed from
Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag
offset programming section). An Almost-Full flag is LOW when the number of
words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y)
for the IDT72V3624, IDT72V3634, or IDT72V3644 respectively. An Almost-
Full flag is HIGH when the number of words in its FIFO is less than or equal
to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT72V3624,
IDT72V3634, or IDT72V3644 respectively. Note that a data word present in
the FIFO output register has been read from memory.
are required after a FIFO read for its Almost-Full flag to reflect the new level
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock
SKEW1
or greater after the read. Otherwise, the subsequent clock cycle
SKEW2
or greater after the write that fills the FIFO to (X+1)
TM
WITH BUS-MATCHING
14
of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-
(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have
not elapsed since the read that reduced the number of words in memory to
[256/512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-
to-HIGH transition of its synchronizing clock after the FIFO read that reduces
the number of words in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH
transition of an Almost-Full flag synchronizing clock begins the first synchro-
nization cycle if it occurs at time t
the number of words in memory to [256/512/1,024-(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figure 25 and 26).
MAILBOX REGISTERS
information between Port A and Port B without putting it in queue. The Mailbox
select (MBA, MBB) inputs choose between a mail register and a FIFO for a
port data transfer operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the
selected Port B bus size is also 36 bits, then the usable width of the Mail1 register
employs data lines A0-A35. If the selected Port B bus size is 18 bits, then the
usable width of the Mail1 Register employs data lines A0-A17. (In this case,
A18-A35 are don’t care inputs.) If the selected Port B bus size is 9 bits, then
the usable width of the Mail1 Register employs data lines A0-A8. (In this case,
A9-A35 are don’t care inputs.)
Register when a Port B write is selected by CSB, W/RB, and ENB with MBB
HIGH. If the selected Port B bus size is also 36 bits, then the usable width of
the Mail2 employs data lines B0-B35. If the selected Port B bus size is 18 bits,
then the usable width of the Mail2 Register employs data lines B0-B17. (In this
case, B18-B35 are don’t care inputs.) If the selected Port B bus size is 9 bits,
then the usable width of the Mail2 Register employs data lines B0-B8. (In this
case, B9-B35 are don’t care inputs.)
LOW. Attempted writes to a mail register are ignored while the mail flag is LOW.
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port Mailbox select input is HIGH.
on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this
case, B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data
are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA
HIGH.
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
when new data is written to the register. The Endian select feature has no effect
on mailbox data. For mail register and Mail Register Flag timing diagrams, see
Figure 27 and 28.
Each FIFO has a 36-bit bypass register to pass command and control
A LOW-to-HIGH transition on CLKA writes data to the Mail 1 Register when
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
Writing data to a mail register sets its corresponding flag (MBF1 or MBF2)
When data outputs of a port are active, the data on the bus comes from the
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
The data in a mail register remains intact after it is read and changes only
COMMERCIAL TEMPERATURE RANGE
SKEW2
or greater after the read that reduces