s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 99

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

8.7.3 ICG Trim Register
TRIM7:TRIM0 — ICG Trim Factor Bits
8.7.4 ICG Trim Value
This register provides non-volatile storage for an optional oscillator trim value, which can be transferred
by the user software to the ICG Trim Register (ICGTR) when the device comes out of reset. (See
ICG Trim
8.7.5 ICG DCO Divider Register
DDIV3:DDIV0 — ICG DCO Divider Control Bits
Freescale Semiconductor
These read/write bits change the size of the internal capacitor used by the internal clock generator. By
testing the frequency of the internal clock and incrementing or decrementing this factor accordingly,
the accuracy of the internal clock can be improved (see
Characteristics). Incrementing this register by one decreases the frequency by 0.195 percent of the
unadjusted value. Decrementing this register by one increases the frequency by 0.195 percent. This
register cannot be written when the CMON bit is set. Reset sets these bits to $80, centering the range
of possible adjustment.
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator.
When ICGON is set, DDIV is controlled by the digital loop filter. The range of valid values for DDIV is
from $0 to $9. Values of $A through $F are interpreted the same as $9. Since the DCO is active during
reset, reset has no effect on DSTG and the value may vary.
Register.)
Address: $0038
Address: $FF80
Address: $0039
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 8-15. ICG DCO Divider Control Register (ICGDVR)
TRIM7
TRIM7
Bit 7
Bit 7
Bit 7
1
1
0
Figure 8-14. Internal Oscillator Trim Value (ICGT)
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
= Unimplemented
TRIM6
Figure 8-13. ICG Trim Register (ICGTR)
TRIM6
6
0
6
0
6
0
TRIM5
TRIM5
5
0
5
0
5
0
TRIM4
TRIM4
4
0
4
0
4
0
U = Unaffected
TRIM3
20.9.1 Trimmed Internal Clock Generator
TRIM3
DDIV3
U
3
0
3
0
3
TRIM2
TRIM2
DDIV2
U
2
0
2
0
2
TRIM1
TRIM1
DDIV1
Input/Output (I/O) Registers
U
1
0
1
0
1
TRIM0
TRIM0
DDIV0
Bit 0
Bit 0
Bit 0
U
0
0
8.7.3
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