adc1215s125hn/c1 NXP Semiconductors, adc1215s125hn/c1 Datasheet
adc1215s125hn/c1
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adc1215s125hn/c1 Summary of contents
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ADC1215S series Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs Rev. 01 — 12 April 2010 1. General description The ADC1215S is a single channel 12-bit Analog-to-Digital ...
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... Digital predistortion loop, power amplifier linearization 4. Ordering information Table 1. Ordering information Type number f (Msps) Package s ADC1215S125HN/C1 125 ADC1215S105HN/C1 105 ADC1215S080HN/C1 80 ADC1215S065HN/C1 65 ADC1215S_SER_1 Preliminary data sheet ADC1215S series; input buffer; CMOS or LVDS DDR digital output Name Description HVQFN40 plastic thermal enhanced very thin quad flat package; no leads ...
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... NXP Semiconductors 5. Block diagram INP INM Fig 1. ADC1215S_SER_1 Preliminary data sheet ADC1215S series; input buffer; CMOS or LVDS DDR digital output ADC1215S CORRECTION AND S/H INPUT INPUT BUFFER STAGE STAGE AND DUTY CYCLE CONTROL Block diagram All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning terminal 1 index area 1 REFB 2 REFT AGND 3 VCM 4 VDDA5V 5 ADC1215S HVQFN40 6 AGND 7 INM INP 8 AGND 9 VDDA3V 10 Transparent top view Fig 2. Pin configuration with CMOS digital outputs selected 6.2 Pin description Table 2. Symbol REFB REFT AGND VCM VDDA5V AGND ...
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... NXP Semiconductors Table 2. Symbol D11 D10 n.c. n.c. DAV n.c. VDDO OGND OTR SCLK/DFS SDIO/ODS CS SENSE VREF [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. Symbol D10_D11_M D10_D11_P D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M D0_D1_P n.c. ADC1215S_SER_1 Preliminary data sheet ADC1215S series ...
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... NXP Semiconductors Table 3. Symbol n.c. DAVM DAVP [1] Pins and pins are the same for both CMOS and LVDS DDR outputs (see [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter Supplies V analog supply voltage 5 V DDA(5V) V analog supply voltage 3 V DDA(3V) V output supply voltage DDO I analog supply current 5 V DDA(5V) I analog supply current 3 V DDA(3V) I output supply current DDO P power dissipation Clock inputs: pins CLKP and CLKM ...
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... NXP Semiconductors Table 6. Static characteristics Symbol Parameter Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level input current IL I HIGH-level input current IH C input capacitance I Digital outputs, CMOS mode: pins D11 to D0, OTR, DAV Output levels, V ...
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... NXP Semiconductors Table 6. Static characteristics Symbol Parameter Accuracy INL integral non-linearity DNL differential non-linearity E offset error offset E gain error G Supply PSRR power supply rejection ratio [1] Typical values measured at V DDA(3V) are across the full temperature range T internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ...
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Dynamic characteristics 10.1 Dynamic characteristics [1] Table 7. Dynamic characteristics Symbol Parameter Conditions Analog signal processing α second MHz 2H i harmonic level MHz MHz 170 ...
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Table 7. Dynamic characteristics …continued Symbol Parameter Conditions IMD Intermodu MHz i lation distortion MHz MHz 170 MHz i [1] Typical values measured ...
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Clock and digital output timing Table 8. Clock and digital output timing characteristics Symbol Parameter Conditions Clock timing input: pins CLKP and CLKM f clock frequency clk t data latency lat(data) time δ clock duty cycle DCS_EN = 1 ...
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Table 8. Clock and digital output timing characteristics Symbol Parameter Conditions LVDS DDR mode timing output: pins D11P to D0P, D11M to D0M, DAVP and DAVM t propagation DATA PD delay DAV t set-up time su t hold time h ...
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... NXP Semiconductors Fig Fig 5. ADC1215S_SER_1 Preliminary data sheet ADC1215S series; input buffer; CMOS or LVDS DDR digital output d(s) t clk CLKP CLKM − 14) DATA DAV t CMOS mode timing d(s) t clk CLKP CLKM − 14 ...
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... NXP Semiconductors 10.3 SPI timings Table 9. Symbol SPI timings t w(SCLK) t w(SCLKH) t w(SCLKL clk(max) [1] Typical values measured at V minimum and maximum values are across the full temperature range T V DDA(3V) CMOS and LVDS interface; unless otherwise specified Fig 6. ADC1215S_SER_1 Preliminary data sheet ADC1215S series ...
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... NXP Semiconductors 11. Application information 11.1 Device control The ADC1215S can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH ...
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... NXP Semiconductors 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. ...
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... NXP Semiconductors The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core ...
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... NXP Semiconductors 11.3 System reference and power management 11.3.1 Internal/external references The ADC1215S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable steps between 0 dB and −6 dB via control bits INTREF[2:0] when bit INTREF_EN = 1 ...
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... NXP Semiconductors VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 12. Internal reference (p-p) full-scale VREF 0.1 μF V SENSE VDDA Fig 14. External reference (p- (p-p) full-scale Figure 12 required reference voltage source. 11.3.2 Reference gain control The reference gain is programmable between − steps via the SPI (see Table 21) ...
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... NXP Semiconductors 11.3.4 Biasing The common-mode input voltage (V buffer bias current can be set to one of three levels (high, medium or low) via the SPI (see Table 11.4 Clock input 11.4.1 Drive modes The ADC1215S can be driven differentially (SINE, LVPECL or LVDS) with little or no degradation on dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor) ...
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... NXP Semiconductors 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via internal 5 kΩ resistors. Fig 18. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI interface (see Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL ...
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... NXP Semiconductors 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see Table Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in OGND/V Each buffer can be loaded by a maximum of 10 pF. ...
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... NXP Semiconductors 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table Fig 20. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver ...
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... NXP Semiconductors Table 13. LVDS_INT_TER[2:0] 101 110 111 11.5.3 Data valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1215S. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in 11.5.4 Out-of-Range (OTR) An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1 ...
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... NXP Semiconductors 11.5.7 Output codes versus input voltage Table 15. − INP < −1 −1.0000000 −0,9995117 −0.9990234 −0.9985352 −0.9980469 .... −0.0009766 −0.0004883 0.0000000 +0.0004883 +0.0009766 .... +0.9980469 +0.9985352 +0.9990234 +0.9995117 +1.0000000 > +1 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1215S serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors ...
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... NXP Semiconductors Table 17 Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows: 1 ...
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... NXP Semiconductors Fig 23. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR Fig 24. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1215S_SER_1 Preliminary data sheet ADC1215S series; input buffer; CMOS or LVDS DDR digital output CS SDIO (CMOS LVDS DDR) ...
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Register allocation map Table 18. Register allocation map Addr Register name R/W Bit definition Hex Bit 7 Bit 6 Bit 5 0005 Reset and R/W SW_RST operating mode 0006 Clock R 0008 Internal R reference ...
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... NXP Semiconductors Table 19. Reset and operating mode control register (address 0005h) bit description Bit Symbol Access 7 SW_RST R RESERVED[2: OP_MODE[1:0] R/W Table 20. Clock control register (address 0006h) bit description Bit Symbol Access SE_SEL R/W 3 DIFF_SE R CLKDIV R/W 0 DCS_EN ...
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... NXP Semiconductors Table 21. Internal reference control register (address 0008h) bit description Bit Symbol Access INTREF_EN R INTREF[2:0] R/W Table 22. Input buffer control register (address 0010h) bit description Bit Symbol IB_IBIAS[1:0] Table 23. Output data standard control register (address 0011h) bit description ...
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... NXP Semiconductors Table 24. Output clock register (address 0012h) bit description Bit Symbol DAVINV DAVPHASE[2:0] Table 25. Offset register (address 0013h) bit description Bit Symbol DIG_OFFSET[5:0] Table 26. Test pattern register 1 (address 0014h) bit description Bit Symbol ...
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... NXP Semiconductors Table 28. Test pattern register 3 (address 0016h) bit description Bit Symbol TESTPAT_USER[3: Table 29. Fast OTR register (address 0017h) bit description Bit Symbol FASTOTR FASTOTR_DET[2:0] Table 30. CMOS output register (address 0020h) bit description Bit Symbol Access ...
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... NXP Semiconductors Table 31. LVDS DDR output register 1 (address 0021h) bit description Bit Symbol Access DAVI_x2_EN R DAVI[1:0] R/W 2 DATAI_x2_EN R DATAI[1:0] R/W Table 32. LVDS DDR output register 2 (address 0022h) bit description Bit Symbol BIT/BYTE_WISE LVDS_INTTER[2:0] ADC1215S_SER_1 Preliminary data sheet ADC1215S series ...
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... NXP Semiconductors 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 0.85 mm terminal 1 index area terminal 1 40 index area Dimensions (1) Unit max 1.00 0.05 0.30 mm nom 0.85 0.02 0.21 0.2 min 0.80 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Revision history Table 33. Revision history Document ID Release date ADC1215S_SER_1 20100412 ADC1215S_SER_1 Preliminary data sheet ADC1215S series; input buffer; CMOS or LVDS DDR digital output Data sheet status Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 April 2010 ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... ADC1215S series; input buffer; CMOS or LVDS DDR digital output NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.2 Clock and digital output timing . . . . . . . . . . . . 12 10 ...