adc1215s125hn/c1 NXP Semiconductors, adc1215s125hn/c1 Datasheet - Page 28

• Manufacturer Part Number: adc1215s125hn/c1
• Description: Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps With Input Buffer; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1215S_SER_1
Preliminary data sheet
Fig 23. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 24. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
(CMOS LVDS DDR)
(CMOS LVDS DDR)
All information provided in this document is subject to legal disclaimers.
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
SDIO
SDIO
CS
CS
Rev. 01 — 12 April 2010
Offset binary, LVDS DDR
default mode at start-up
two's complement, CMOS
default mode at start-up
ADC1215S series
© NXP B.V. 2010. All rights reserved.
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