adc1215s125hn/c1 NXP Semiconductors, adc1215s125hn/c1 Datasheet - Page 21

• Manufacturer Part Number: adc1215s125hn/c1
• Description: Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps With Input Buffer; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1215S_SER_1
Preliminary data sheet
11.3.4 Biasing
11.4.1 Drive modes
11.4 Clock input
The common-mode input voltage (V
buffer bias current can be set to one of three levels (high, medium or low) via the SPI
(see
The ADC1215S can be driven differentially (SINE, LVPECL or LVDS) with little or no
degradation on dynamic performances. It can also be driven by a single-ended LVCMOS
signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or
CLKM (CLKP should be connected to ground via a capacitor).
Fig 16. LVCMOS single-ended clock input
Fig 17. Differential clock input
Table
a. Rising edge LVCMOS
a. Sine clock input
c. LVDS clock input
clock input
clock input
22).
clock input
LVCMOS
LVDS
Sine
All information provided in this document is subject to legal disclaimers.
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
Rev. 01 — 12 April 2010
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CLKM
CLKP
CLKM
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CLKP
CLKM
CLKP
I(cm)
) on pins INP and INM is set internally. The input
clock input
b. Falling edge LVCMOS
b. Sine clock input (with transformer)
d. LVPECL clock input
ADC1215S series
Sine
clock input
LVCMOS
clock input
LVPECL
© NXP B.V. 2010. All rights reserved.
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CLKM
CLKP
CLKM
CLKP
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CLKM
CLKP
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