adc1215s125hn/c1 NXP Semiconductors, adc1215s125hn/c1 Datasheet - Page 24

• Manufacturer Part Number: adc1215s125hn/c1
• Description: Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps With Input Buffer; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1215S_SER_1
Preliminary data sheet
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1
(see
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side
Table
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see
voltage levels.
Table 13.
LVDS_INT_TER[2:0]
000
001
010
011
100
Fig 20. LVDS DDR digital output buffer - externally terminated
Fig 21. LVDS DDR digital output buffer - internally terminated
(Figure
Table
32).
LVDS DDR output register 2
23).
20) or internally via SPI control bits LVDS_INT_TER[2:0] (see
All information provided in this document is subject to legal disclaimers.
−
+
−
+
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
Rev. 01 — 12 April 2010
3.5 mA
typ
3.5 mA
typ
100 Ω
+
+
−
−
VCCO
D
D
VCCO
D
D
OGND
OGND
n
n
x
x
P/D
M/D
P/D
M/D
Table
x + 1
n + 1
x + 1
n + 1
Resistor value (Ω)
no internal termination
300
180
110
150
P
P
M
M
31) in order to adjust the output logic
ADC1215S series
100 Ω
RECEIVER
RECEIVER
005aaa058
005aaa059
© NXP B.V. 2010. All rights reserved.
Figure 21
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and