adc1215s125hn/c1 NXP Semiconductors, adc1215s125hn/c1 Datasheet - Page 15

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adc1215s125hn/c1

Manufacturer Part Number
adc1215s125hn/c1
Description
Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps With Input Buffer; Cmos Or Lvds Ddr Digital Outputs
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
ADC1215S_SER_1
Preliminary data sheet
10.3 SPI timings
Table 9.
[1]
Symbol
SPI timings
t
t
t
t
t
f
w(SCLK)
w(SCLKH)
w(SCLKL)
su
h
clk(max)
Fig 6.
Typical values measured at V
minimum and maximum values are across the full temperature range T
V
CMOS and LVDS interface; unless otherwise specified
DDA(3V)
SPI timing
SCLK
Characteristics
SDIO
= 3 V, V
Parameter
SCLK pulse width
SCLK pulse width HIGH
SCLK pulse width LOW
set-up time
hold time
maximum clock frequency
CS
All information provided in this document is subject to legal disclaimers.
DDO
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
t
su
= 1.8 V, V
R/W
Rev. 01 — 12 April 2010
DDA(3V)
W1
DDA(5V)
t
h
t
su
= 3 V, V
= 5 V, V
W0
t
w(SCLK)
DDO
A12
INP
Conditions
data to SCLKH
CS to SCLKH
data to SCLKH
CS to SCLKH
= 1.8 V, V
− V
INM
A11
t
= −1 dBFS; internal reference mode; applied to
w(SCLKL)
DDA(5V)
ADC1215S series
t
w(SCLKH)
D2
= 5 V; T
amb
40
16
16
5
2
-
Min
5
2
D1
amb
= −40 °C to +85 °C at
= 25 °C and C
Typ
-
-
-
-
-
-
-
-
D0
© NXP B.V. 2010. All rights reserved.
t
h
005aaa065
Max
-
-
-
-
-
-
-
25
L
= 5 pF;
15 of 39
Unit
ns
ns
ns
ns
ns
ns
ns
MHz

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